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1. RAGUL_T_RISCV_SOC_TAPEOUT_VSD RAGUL_T_RISCV_SOC_TAPEOUT_VSD Public

   This repository documents my weekly progress in the RISC-V Reference SoC Tapeout Program, covering RTL design, verification, synthesis, DFT, physical design, STA, and tapeout using open-source EDA …

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2. RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_1 RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_1 Public

   Welcome to Week 1 of our journey into Digital Design & RTL Implementation. This week emphasizes understanding digital fundamentals, combinational and sequential circuits, and practical RTL coding w…

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3. RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_2 RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_2 Public

   Learn the basics of System-on-Chip (SoC) design, including CPU, memory, peripherals, and interconnect. Explore BabySoC, a simplified SoC model for learning, and understand the importance of functio…

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4. RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_3 RAGUL_T_RISCV_SOC_TAPEOUT_VSD_Week_3 Public

5. Real-Time-Collision-Detection-System-Using-Arty-S7-FPGA-Laser-Ranging-Sensor Real-Time-Collision-Detection-System-Using-Arty-S7-FPGA-Laser-Ranging-Sensor Public

   Real-Time Collision Detection System using Arty S7 FPGA and VL53L0X LiDAR sensor. Implements an AXI-based MicroBlaze soft processor for I2C communication to measure distance and trigger alerts. Des…

   Python 3

6. 4bit-ALU-Spartan6 4bit-ALU-Spartan6 Public

   Forked from Senbagaseelan18/4bit-ALU-Spartan6

   A 4-bit ALU in VHDL for Spartan-6 FPGA, tested with onboard switches and LEDs, verified in Vivado and hardware.

   VHDL 1