Verilator testbench for Top.v; builds with -Wno-UNSIGNED#134
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PreethamKoundinyaGajulamandyam wants to merge 1 commit intoRivier-Computer-Science:mainfrom
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Generate C++ from Top.v
verilator --cc RTL/Chisel/generators/generated/verilog_hierarchical_timed_rtl/Top.v
--exe RTL/verilator_testbench/pipeline_testbench.cpp
--trace -Wno-UNSIGNED
Build
make -C obj_dir -f VTop.mk -j"$(nproc)"
Run (example)
./obj_dir/VTop +MAX_CYCLES=2000 +WAVES