🧠 32-RAM Verification using SV Testbench

This repo contains a verification environment for a custom 32RAM design using SystemVerilog in QuestaSim. The goal of this project was to validate the functionality of a synchronous RAM using a modular and reusable testbench architecture.

📌 Highlights

• 🛠 Design: A parameterized RAM module with read/write enable, address decoding, and synchronous reset.
• ✅ Verification: Testbench developed in SystemVerilog with constrained-random stimulus and functional coverage.
• 📊 Outputs: Waveform analysis and code/functional coverage reports.
• 🧪 Test Strategy: Includes directed and random tests for edge cases such as:
  • Read-before-write
  • Write enable glitches
  • Out-of-bound addresses
  • Reset behavior

📌 RAM Architecture

📌 SV Architecture

📌 Outputs and Coverage Reports

Output Terminal Observations:

Questa Coverage Report: