Add RISC-V and RVV1.0 support into library#1
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suvorovrain wants to merge 28 commits intoSparseLinearAlgebra:devfrom
Open
Add RISC-V and RVV1.0 support into library#1suvorovrain wants to merge 28 commits intoSparseLinearAlgebra:devfrom
suvorovrain wants to merge 28 commits intoSparseLinearAlgebra:devfrom
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RISC-V cpufeatures
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Also add RISC-V support in CMake with cpu_features |
gsvgit
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Feb 9, 2025
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Is there documentation where information about RVV support should be added?
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| bool cpu_features_avx2 ; // x86_64 with AVX2 | ||
| bool cpu_features_avx512f ; // x86_64 with AVX512f | ||
| bool cpu_features_rvv ; // RISC-V with RVV1.0 |
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Should it be cpu_features_rvv_1_0 or something else to note that it may be incompatible with 0.7 ?
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I haven't found it. So I've searched for every part of code in library where was implemented AVX support and add RVV following the example of how AVX support was done |
vkutuev
requested changes
Feb 10, 2025
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| #if GB_COMPILER_SUPPORTS_RVV1 | ||
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| GB_TARGET_AVX2 static inline void GB_AxB_saxpy5_unrolled_rvv |
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| CPU_FEATURES_END_CPP_NAMESPACE | ||
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| #endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ No newline at end of file |
| } | ||
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| #endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) | ||
| #endif // CPU_FEATURES_ARCH_RISCV No newline at end of file |
Update global value
gsvgit
approved these changes
Feb 13, 2025
vkutuev
approved these changes
Feb 13, 2025
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Implement support of RISC-V architecture and RVV1.0 RISC-V vector extension into library.
Add saxpy function that uses RVV1.0 instruction set.