perf: turbo VEC flash attention — +9% decode on CUDA via autoresearch

[signalnine]

Summary

+8-9% turbo3 decode throughput on CUDA + auto-fix for Qwen symmetric turbo3.

Speed (RTX 5090, clean A/B on upstream HEAD)

Model	Upstream	PR	Speedup
Qwen2.5-7B turbo3 (auto-asym)	248.7	272.1	+9.4%
Mistral-7B turbo3 symmetric	239.4	260.4	+8.8%

Quality: zero regression

• PPL: Qwen +1.7%, Mistral +2.1% (vs fp16, unchanged from upstream)
• NIAH: 5/5 on both models

Changes

1. FA optimizations (fattn-vec.cuh): nthreads_KQ=1, nthreads_V/=8, warp shuffle KQ, skip sparse V check, precomputed V centroids, __expf, occupancy 2. Found via autoresearch (59 experiments overnight).
2. Shmem KQ LUT (fattn-vec.cuh): precompute Q×centroid once in shmem, eliminate per-element multiply. Ported from PR perf: FA kernel optimizations + auto-asymmetric KV + warp shuffle WHT #36 (credit: Madreag/turbo3-cuda).
3. Auto-asymmetric GQA fix (llama-kv-cache.cpp): auto-upgrade K→q8_0 when GQA≥6:1. Fixes Qwen symmetric turbo3 (PPL 2887→7.98). See Symmetric turbo3 KV catastrophic on Qwen2.5 (GQA 7:1) — auto-asymmetric fix proposed #54.
4. HIP build fix (turbo-quant.cuh): suppress -Wnodiscard warnings.
5. Autoresearch framework (scripts/autoresearch/): automated CUDA kernel optimization harness.

Test plan

• Clean A/B speed (+9% Qwen, +9% Mistral)
• PPL zero regression (wikitext-2, 10 chunks)
• NIAH 5/5 (Kamradt varied filler, both models)
• Auto-asymmetric: Qwen PPL 2887→7.98
• Mistral unaffected by auto-asymmetric (GQA 4:1)
• HIP -Werror build fix
• Ampere (sm_86) testing

[signalnine]

Updated: +15.3% decode with shmem LUT

Correction: The 15.3% number was from runs at different thermal states. Clean A/B on same session shows +9% total (see final results below). The shmem LUT adds ~2% on top of the autoresearch optimizations.

[signalnine]

Final Results — Clean A/B on upstream HEAD (bc05a68)

All benchmarks back-to-back, same GPU thermal state, llama-bench -r 3.

Speed (RTX 5090, tg128, -p 0 -n 128)

Model	Config	Upstream	PR #53	Speedup
Qwen2.5-7B Q4_0	turbo3 (auto→q8_0-K)	248.7	272.1	+9.4%
Qwen2.5-7B Q4_0	turbo3 (forced sym)	248.7	267.3	+7.5%
Mistral-7B Q4_0	turbo3 symmetric	239.4	260.4	+8.8%

PPL (wikitext-2-raw, 10 chunks)

Model	Config	PPL	Δ vs fp16 baseline
Qwen2.5-7B	fp16 baseline	7.85	—
Qwen2.5-7B	turbo3 (auto-asymmetric)	7.98	+1.7%
Mistral-7B	fp16 baseline	8.39	—
Mistral-7B	turbo3 symmetric	8.57	+2.1%

NIAH (Kamradt varied filler, 5 depths)

Model	Config	Score
Qwen2.5-7B	turbo3 (auto-asymmetric)	5/5
Mistral-7B	turbo3 symmetric	5/5

What's in this PR

1. FA kernel optimizations (fattn-vec.cuh): nthreads_KQ=1, nthreads_V/=8, warp shuffle KQ, sparse V skip, precomputed V centroids, __expf, occupancy 2
2. Shared-memory KQ LUT (fattn-vec.cuh): precompute Q×centroid in shmem, eliminate per-element multiply in KQ inner loop
3. Auto-asymmetric GQA fix (llama-kv-cache.cpp): auto-upgrade K to q8_0 when GQA ≥ 6:1 — fixes Qwen symmetric turbo3 (PPL 2887→7.98)
4. HIP build fix (turbo-quant.cuh): suppress -Wnodiscard on unchecked cudaMemcpy calls
5. Autoresearch framework (scripts/autoresearch/): automated kernel optimization harness

[seanrasch]

Heads up — PR doesn't build standalone against feature/turboquant-kv-cache HEAD (bc05a6803). Looks like a squash dropped the GGML_TYPE_TQ4_0 enum declaration.

ggml/include/ggml.h still ends at GGML_TYPE_TQ2_0 = 35, but ggml/src/ggml-cpu/ops.cpp references GGML_TYPE_TQ4_0 in 7 switch cases (lines 683, 1136, 1268, 4359, 4638, 4864, 5600), and ggml/src/ggml-turbo-quant.c uses TQ4_0_CENTROIDS. Build error on RTX 3080 Ti / SM 8.6 / GCC 12.4:

ggml/src/ggml-cpu/ops.cpp:683:14: error: 'GGML_TYPE_TQ4_0' was not declared in this scope; did you mean 'GGML_TYPE_TQ2_0'?

Either the enum addition needs to come back, or the switch cases / centroid table belong on a branch that has it (PR #45 doesn't add it either, so it's not a missing dependency on #45).

Happy to benchmark the VEC FA + SMEM LUT optimizations on Ampere once it builds — interested in whether the +15% decode claim holds up at SM 8.6 (our PR #36 test was a wash on Ampere, so concrete numbers would be useful).

[signalnine]

Good catch — the 7 GGML_TYPE_TQ4_0 switch cases in ops.cpp leaked from our experimental weight compression branch. TQ4_0 was a prototype format (WHT + uniform q4_0, see optimization log) that never shipped. Removed in bb3a6eb.

The TQ4_0_CENTROIDS table in turbo-quant.c is upstream — that's the Lloyd-Max centroid table name used internally by TQ4_1S quantize/dequant (confusing name, but it's TheTom's code, not ours).

Should build clean now. Would love Ampere numbers — our +9% was Blackwell-only. The shmem LUT and nthreads tuning may behave differently on SM 8.6 with its smaller L1 and different warp scheduler.

[signalnine]

RTX 3090 (Ampere, sm_86) Validation

Tested on RunPod RTX 3090 24 GB, CUDA 12.4. Qwen2.5-7B-Instruct Q4_K_M.

Speed

KV Config	pp512	pp2K	pp8K	pp32K	tg128	vs f16 tg
f16	5,635	5,582	4,987	3,456	147.8	—
q4_0	5,488	5,461	4,884	3,391	141.4	-4.3%
turbo3	5,380	5,317	4,752	3,320	139.9	-5.3%
turbo2	5,383	5,327	4,769	3,338	142.3	-3.7%

Quality (PPL @2k, 10 chunks)

KV Config	PPL	vs f16
f16	5.754	—
q4_0	9,714	catastrophic (GQA 7:1)
turbo3	5.762	+0.1%
turbo2	5.870	+2.0%

KLD (ctx=2048, 5 chunks)

KV Config	Mean KLD
q4_0	7.584 (broken)
turbo3	0.024

Key findings

• Auto-asymmetric is critical on Ampere: q4_0 KV (4-bit K+V) is catastrophically broken on Qwen's 7:1 GQA — PPL 9,714. turbo3 with auto-asymmetric (q8_0 K, turbo3 V) gives PPL 5.762, within 0.1% of f16.
• Consistent overhead across architectures: ~5% prefill and decode overhead matches RTX 5090 (Blackwell) results.
• turbo2 is viable on Ampere: PPL 5.870 (+2%), faster decode than turbo3 (142 vs 140 t/s).