UBC ORCA Lab
- 11 followers
- UBC, Vancouver, Canada
- lemieux@ece.ubc.ca
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RISC-V_Summit_2024
RISC-V_Summit_2024 PublicFor uploading relevant documents for the 2024 North America RISC-V Summit.
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vbx-mxp-linux-xlnx
vbx-mxp-linux-xlnx PublicForked from Xilinx/linux-xlnx
The official Linux kernel from Xilinx
C 1
Repositories
- cve2-RV64 Public Forked from openhwgroup/cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
UBC-ORCA/cve2-RV64’s past year of commit activity - riscv-debug-tutorial Public
An end-to-end tutorial explaining how RISC-V run-control debug works: how GDB, OpenOCD, the Debug Transport Module, and the Debug Module fit together with a CV32E20 soft core, plus a section on what a textbook single-cycle CPU would need to support the same debug stack.
UBC-ORCA/riscv-debug-tutorial’s past year of commit activity - Gatling-V Public template
UBC-ORCA/Gatling-V’s past year of commit activity - Design_Examples Public Forked from fpgacademy/Design_Examples
Sample systems for use on the DE-Series boards
UBC-ORCA/Design_Examples’s past year of commit activity - cx_runtime Public
UBC-ORCA/cx_runtime’s past year of commit activity
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