Add Makefile.sv to directly simulate SV files using tools like VCS#38
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filamoon wants to merge 1 commit intoadam-maj:masterfrom
Open
Add Makefile.sv to directly simulate SV files using tools like VCS#38filamoon wants to merge 1 commit intoadam-maj:masterfrom
filamoon wants to merge 1 commit intoadam-maj:masterfrom
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So no need to use other tools to first convert SV to verilog.