Skip to content

Rename .bssnz to .noinit to fix linker wildcard conflicts #3685

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wiktorkwiatkowski wants to merge 1 commit into
base: master
Choose a base branch
from
+856 −856
Open

Rename .bssnz to .noinit to fix linker wildcard conflicts #3685

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions boot/startup/include/mynewt_config.ld.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,8 @@
#ifndef BSS_RAM
#define BSS_RAM RAM
#endif
#ifndef BSSNZ_RAM
#define BSSNZ_RAM RAM
#ifndef NOINIT_RAM
#define NOINIT_RAM RAM
#endif

#ifndef MYNEWT_VAL_RESET_HANDLER
Expand Down
18 changes: 9 additions & 9 deletions boot/startup/mynewt_cortex_m0.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,6 @@ SECTIONS
__data_image__ = LOADADDR(.data);
_sidata = LOADADDR(.data);

.bssnz (NOLOAD) :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > BSSNZ_RAM

#ifdef COREBSS_RAM
.corebss (NOLOAD):
{
Expand All @@ -296,6 +287,15 @@ SECTIONS
__bss_end__ = .;
} > BSS_RAM

.noinit (NOLOAD) :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > NOINIT_RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
18 changes: 9 additions & 9 deletions boot/startup/mynewt_cortex_m3.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,6 @@ SECTIONS
__data_image__ = LOADADDR(.data);
_sidata = LOADADDR(.data);

.bssnz (NOLOAD) :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > BSSNZ_RAM

#ifdef COREBSS_RAM
.corebss (NOLOAD):
{
Expand All @@ -296,6 +287,15 @@ SECTIONS
__bss_end__ = .;
} > BSS_RAM

.noinit (NOLOAD) :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > NOINIT_RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
18 changes: 9 additions & 9 deletions boot/startup/mynewt_cortex_m33.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,6 @@ SECTIONS
__data_image__ = LOADADDR(.data);
_sidata = LOADADDR(.data);

.bssnz (NOLOAD) :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > BSSNZ_RAM

#ifdef COREBSS_RAM
.corebss (NOLOAD):
{
Expand All @@ -296,6 +287,15 @@ SECTIONS
__bss_end__ = .;
} > BSS_RAM

.noinit (NOLOAD) :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > NOINIT_RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
18 changes: 9 additions & 9 deletions boot/startup/mynewt_cortex_m4.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,6 @@ SECTIONS
__data_image__ = LOADADDR(.data);
_sidata = LOADADDR(.data);

.bssnz (NOLOAD) :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > BSSNZ_RAM

#ifdef COREBSS_RAM
.corebss (NOLOAD):
{
Expand All @@ -296,6 +287,15 @@ SECTIONS
__bss_end__ = .;
} > BSS_RAM

.noinit (NOLOAD) :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > NOINIT_RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
18 changes: 9 additions & 9 deletions boot/startup/mynewt_cortex_m7.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,6 @@ SECTIONS
__data_image__ = LOADADDR(.data);
_sidata = LOADADDR(.data);

.bssnz (NOLOAD) :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > BSSNZ_RAM

#ifdef COREBSS_RAM
.corebss (NOLOAD):
{
Expand All @@ -296,6 +287,15 @@ SECTIONS
__bss_end__ = .;
} > BSS_RAM

.noinit (NOLOAD) :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > NOINIT_RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
22 changes: 11 additions & 11 deletions hw/bsp/ada_feather_nrf52/ada_feather_nrf52_no_boot.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,8 @@ MEMORY
* __StackLimit
* __StackTop
* __stack
* __bssnz_start__
* __bssnz_end__
* __noinit_start__
* __noinit_end__
*/
ENTRY(Reset_Handler)

Expand Down Expand Up @@ -149,15 +149,6 @@ INCLUDE "link_tables.ld.h"
* caveat:
* 1. It does not get zeroed at init-time.
*/
.bssnz :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > RAM

.bss :
{
. = ALIGN(4);
Expand All @@ -168,6 +159,15 @@ INCLUDE "link_tables.ld.h"
__bss_end__ = .;
} > RAM

.noinit :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
4 changes: 2 additions & 2 deletions hw/bsp/ada_feather_nrf52/include/bsp/bsp.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,10 @@ extern "C" {
/* Define special stackos sections */
#define sec_data_core __attribute__((section(".data.core")))
#define sec_bss_core __attribute__((section(".bss.core")))
#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
#define sec_noinit __attribute__((section(".noinit")))

/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
#define bssnz_t sec_noinit

extern uint8_t _ram_start;
#define RAM_SIZE 0x10000
Expand Down
22 changes: 11 additions & 11 deletions hw/bsp/ada_feather_nrf52/split_ada_feather_nrf52.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,8 @@ MEMORY
* __StackLimit
* __StackTop
* __stack
* __bssnz_start__
* __bssnz_end__
* __noinit_start__
* __noinit_end__
*/
ENTRY(Reset_Handler_split)

Expand Down Expand Up @@ -162,15 +162,6 @@ INCLUDE "link_tables.ld.h"
* This section exists because of a hardware defect; see errata 33 and 34
* in nrf52 errata sheet.
*/
.bssnz :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > RAM

.bss :
{
. = ALIGN(4);
Expand All @@ -181,6 +172,15 @@ INCLUDE "link_tables.ld.h"
__bss_end__ = .;
} > RAM

.noinit :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
4 changes: 2 additions & 2 deletions hw/bsp/ada_feather_stm32f405/include/bsp/bsp.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,10 @@ extern "C" {
/* Define special stackos sections */
#define sec_data_core __attribute__((section(".data.core")))
#define sec_bss_core __attribute__((section(".bss.core")))
#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
#define sec_noinit __attribute__((section(".noinit")))

/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
#define bssnz_t sec_noinit

extern uint8_t _ram_start;
extern uint8_t _ccram_start;
Expand Down
4 changes: 2 additions & 2 deletions hw/bsp/ada_feather_stm32f405/link/include/mcu_config.ld.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,13 @@
* Memory regions placed in CCM
* If stack or core data or other section should be place in RAM
* <target_name>/link/include/target_config.ld.h should just do:
* #undef BSSNZ_RAM
* #undef NOINIT_RAM
* #undef COREBSS_RAM
* #undef COREDATA_RAM
* #undef STACK_REGION
*/

#define BSSNZ_RAM CCM
#define NOINIT_RAM CCM
#define COREBSS_RAM CCM
#define COREDATA_RAM CCM
#define STACK_REGION CCM
4 changes: 2 additions & 2 deletions hw/bsp/apollo2_evb/include/bsp/bsp.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,10 +28,10 @@ extern "C" {
/* Define special stackos sections */
#define sec_data_core __attribute__((section(".data.core")))
#define sec_bss_core __attribute__((section(".bss.core")))
#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
#define sec_noinit __attribute__((section(".noinit")))

/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
#define bssnz_t sec_noinit

extern uint8_t _ram_start;

Expand Down
4 changes: 2 additions & 2 deletions hw/bsp/apollo3_evb/include/bsp/bsp.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,10 @@ extern "C" {
/* Define special stackos sections */
#define sec_data_core __attribute__((section(".data.core")))
#define sec_bss_core __attribute__((section(".bss.core")))
#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
#define sec_noinit __attribute__((section(".noinit")))

/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
#define bssnz_t sec_noinit

extern uint8_t _ram_start;

Expand Down
4 changes: 2 additions & 2 deletions hw/bsp/arduino_primo_nrf52/include/bsp/bsp.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,10 @@ extern "C" {
/* Define special stackos sections */
#define sec_data_core __attribute__((section(".data.core")))
#define sec_bss_core __attribute__((section(".bss.core")))
#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
#define sec_noinit __attribute__((section(".noinit")))

/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
#define bssnz_t sec_noinit

extern uint8_t _ram_start;
#define RAM_SIZE 0x10000
Expand Down
22 changes: 11 additions & 11 deletions hw/bsp/arduino_primo_nrf52/primo_no_boot.ld
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,8 @@ MEMORY
* __StackLimit
* __StackTop
* __stack
* __bssnz_start__
* __bssnz_end__
* __noinit_start__
* __noinit_end__
*/
ENTRY(Reset_Handler)

Expand Down Expand Up @@ -149,15 +149,6 @@ INCLUDE "link_tables.ld.h"
* caveat:
* 1. It does not get zeroed at init-time.
*/
.bssnz :
{
. = ALIGN(4);
__bssnz_start__ = .;
*(.bss.core.nz*)
. = ALIGN(4);
__bssnz_end__ = .;
} > RAM

.bss :
{
. = ALIGN(4);
Expand All @@ -168,6 +159,15 @@ INCLUDE "link_tables.ld.h"
__bss_end__ = .;
} > RAM

.noinit :
{
. = ALIGN(4);
__noinit_start__ = .;
*(.noinit*)
. = ALIGN(4);
__noinit_end__ = .;
} > RAM

/* Heap starts after BSS */
. = ALIGN(8);
__HeapBase = .;
Expand Down
Loading
Loading