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[BREAKING CHANGE] reorganize and unify STM32 ports #19004

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adaa38a
boards/arm/stm32f4: drop duplicated STM32_ROMFS, use common board logic
raiden00pl May 31, 2026
81b30bb
boards/arm/stm32{f1,f4}: drop duplicated reset.c/romfs, use common bo…
raiden00pl Jun 1, 2026
88747d5
arch/arm/src/stm32l4: use common/stm32 1-Wire driver
raiden00pl Jun 3, 2026
f7d6838
arch/arm/src/stm32: unify LSI driver and make RCC headers per-family
raiden00pl Jun 3, 2026
6dfcc4c
arch/arm/src/stm32: unify timer driver across all families
raiden00pl Jul 4, 2026
afbf64e
arch/arm/src/stm32: unify TIM free-running wrapper into common/stm32
raiden00pl Jun 5, 2026
c95e84b
arch/arm/src/stm32: unify TIM one-shot wrapper into common/stm32
raiden00pl Jun 5, 2026
61ea10c
arch/arm/src/stm32: unify TIM1/TIM8 interrupt vector names across fam…
raiden00pl Jun 5, 2026
a265c0a
arch/arm/src/stm32: unify quadrature encoder driver into common/stm32
raiden00pl Jun 5, 2026
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44 changes: 7 additions & 37 deletions .github/CODEOWNERS
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80 changes: 59 additions & 21 deletions Documentation/guides/stm32_ports.rst
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4 changes: 2 additions & 2 deletions arch/arm/include/stm32c0/irq.h
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Expand Up @@ -86,8 +86,8 @@
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/include/stm32f0/irq.h
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Expand Up @@ -91,8 +91,8 @@
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
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4 changes: 2 additions & 2 deletions arch/arm/include/stm32g0/irq.h
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Expand Up @@ -119,8 +119,8 @@
# define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
#endif

#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */

#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
defined(CONFIG_ARCH_CHIP_STM32G070RB)
Expand Down
16 changes: 8 additions & 8 deletions arch/arm/include/stm32h5/stm32h5xx_irq.h
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Expand Up @@ -88,10 +88,10 @@
# define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */
# define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */
# define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */
# define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
# define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
# define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
# define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
# define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
# define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
# define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
# define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
Expand All @@ -112,10 +112,10 @@
# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 62) /* 62: UART5 global interrupt */
# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */
# define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */
# define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */
# define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */
# define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */
# define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */
# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */
# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */
# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */
# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */
# define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */
# define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */
# define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */
Expand Down
3 changes: 3 additions & 0 deletions arch/arm/include/stm32h7/chip.h
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Expand Up @@ -247,6 +247,9 @@
# error STM32 H7 chip Family not identified
#endif

#define STM32_NATIM 2 /* Advanced timers TIM1 and TIM8 */
#define STM32_NBTIM 2 /* Basic timers TIM6 and TIM7 */

/* TBD FPU Configuration */

#if defined(CONFIG_ARCH_HAVE_FPU)
Expand Down
16 changes: 8 additions & 8 deletions arch/arm/include/stm32l5/stm32l562xx_irq.h
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Expand Up @@ -91,20 +91,20 @@
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */
#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */
#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */
#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */
#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */
Expand Down
16 changes: 8 additions & 8 deletions arch/arm/include/stm32n6/stm32n6xx_irq.h
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Expand Up @@ -145,20 +145,20 @@
#define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 109) /* 109: I3C1 error interrupt */
#define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 110) /* 110: I3C2 event interrupt */
#define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 111) /* 111: I3C2 error interrupt */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */
#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */
#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 116) /* 116: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 117) /* 117: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 118) /* 118: TIM4 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 119) /* 119: TIM5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 120) /* 120: TIM6 global interrupt */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 121) /* 121: TIM7 global interrupt */
#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */
#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */
#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */
#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 126) /* 126: TIM9 global interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 127) /* 127: TIM10 global interrupt */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 128) /* 128: TIM11 global interrupt */
Expand Down
16 changes: 8 additions & 8 deletions arch/arm/include/stm32u5/stm32u5xx_irq.h
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Expand Up @@ -90,28 +90,28 @@
#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */
#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */
#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */
#define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */
#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */
#define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 transition error */
#define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 index error */
#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 53) /* 53: TIM8 direction change interrupt */
#define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 53) /* 53: TIM8 index */
#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */
#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */
#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */
Expand Down
2 changes: 2 additions & 0 deletions arch/arm/include/stm32wb/chip.h
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Expand Up @@ -47,6 +47,8 @@
# define STM32_NGTIM16 0 /* No 16-bit general timers */
#endif

#define STM32_NGTIM (STM32_NGTIM16 + STM32_NGTIM32)

#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55)
# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */
# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */
Expand Down
1 change: 1 addition & 0 deletions arch/arm/include/stm32wl5/chip.h
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Expand Up @@ -44,6 +44,7 @@
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NUSART 2 /* USART 1-2 */
Expand Down
58 changes: 25 additions & 33 deletions arch/arm/src/common/stm32/CMakeLists.txt
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Expand Up @@ -33,19 +33,42 @@ set(SRCS)

list(APPEND SRCS stm32_waste.c)
list(APPEND SRCS stm32_uid.c)
list(APPEND SRCS stm32_lsi.c)

if(CONFIG_TIMER AND CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim_lowerhalf.c)
endif()

if(CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim.c)
endif()

if(CONFIG_STM32_FREERUN)
list(APPEND SRCS stm32_freerun.c)
endif()

if(CONFIG_STM32_ONESHOT)
list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c)
endif()
if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE)
list(APPEND SRCS stm32_qencoder.c)
endif()

if(CONFIG_STM32_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()

if(CONFIG_STM32_1WIREDRIVER)
list(APPEND SRCS stm32_1wire_m3m4_v1.c)
endif()

if(CONFIG_STM32_COMMON_LEGACY)
list(
APPEND
SRCS
stm32_allocateheap_m3m4_v1.c
stm32_start_m3m4_v1.c
stm32_lse_m3m4_v1.c
stm32_lsi_m3m4_v1.c
stm32_irq_m3m4_v1.c
stm32_capture_m3m4_v1.c)

Expand All @@ -72,10 +95,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
list(APPEND SRCS stm32_sdio_m3m4_v1.c)
endif()

if(CONFIG_STM32_HAVE_IP_TIMERS)
list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c)
endif()

if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1)
list(APPEND SRCS stm32_ccm_m3m4_v1.c)
endif()
Expand Down Expand Up @@ -147,18 +166,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
endif()
endif()

if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS)
list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c)
endif()

if(CONFIG_STM32_ONESHOT)
list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c)
endif()

if(CONFIG_STM32_FREERUN)
list(APPEND SRCS stm32_freerun_m3m4_v1.c)
endif()

if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
if(CONFIG_STM32_I2C_ALT)
list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c)
Expand Down Expand Up @@ -261,10 +268,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
list(APPEND SRCS stm32_hrtim_m3m4_v1.c)
endif()

if(CONFIG_STM32_1WIREDRIVER)
list(APPEND SRCS stm32_1wire_m3m4_v1.c)
endif()

if(CONFIG_STM32_HCIUART)
list(APPEND SRCS stm32_hciuart_m3m4_v1.c)
endif()
Expand All @@ -289,10 +292,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c)
endif()

if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE)
list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c)
endif()

if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)
if(CONFIG_STM32_CAN_CHARDRIVER)
list(APPEND SRCS stm32_can_m3m4_v1.c)
Expand Down Expand Up @@ -356,7 +355,7 @@ if(CONFIG_STM32_COMMON_LEGACY)
endif()

if(CONFIG_ARCH_CORTEXM0)
list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c)
list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c)

if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1)
list(APPEND SRCS stm32_gpio_m0_v1.c)
Expand Down Expand Up @@ -462,10 +461,6 @@ if(CONFIG_ARCH_CORTEXM0)
list(APPEND SRCS stm32_rng_m0_v1.c)
endif()

if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1)
list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c)
endif()

if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1)
list(APPEND SRCS stm32_iwdg_m0_v1.c)
endif()
Expand All @@ -483,9 +478,6 @@ if(CONFIG_ARCH_CORTEXM0)
endif()
endif()

if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32_qencoder_m0_v1.c)
endif()
endif()

if(CONFIG_SENSORS_HALL3PHASE)
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13 changes: 13 additions & 0 deletions arch/arm/src/common/stm32/Kconfig.have
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Expand Up @@ -1007,6 +1007,19 @@ config STM32_HAVE_TIM19
config STM32_HAVE_TIM20
bool

# Timer counter width. TIM2 and TIM5 are 32-bit on most families; these
# capability flags carry that per-family knowledge so the common timer
# lower-half driver does not need chip-line #ifdefs. A family whose TIM2 or
# TIM5 is 32-bit selects the matching flag from its chip Kconfig; every other
# timer (and the 16-bit STM32F10xx/STM32L15xx/STM32F30xx/Cortex-M0 lines) is
# left at the default 16-bit width.

config STM32_HAVE_TIM2_32BITS
bool

config STM32_HAVE_TIM5_32BITS
bool

config STM32_HAVE_LPTIM1
bool

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