arm/rm57: Add support for TI Hercules RM57 and LaunchXL2 board

Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst

@@ -0,0 +1,115 @@
+=====================
+LAUNCHXL2-RM57L
+=====================
+
+.. tags:: chip:rm57, arch:armv7-r, vendor:ti
+
+The `LAUNCHXL2-RM57L <https://www.ti.com/tool/LAUNCHXL2-RM57L>`__ is a
+LaunchPad-format evaluation board from Texas Instruments built around the
+Hercules RM57L843 safety microcontroller (dual Cortex-R5F cores in
+lockstep). It's aimed at evaluating TI's Hercules safety MCU family rather
+than any particular application.
+
+.. warning::
+
+   This board port is new and experimental. Only the serial console (SCI1)
+   and the two user LEDs are currently supported; pin-mux configuration,
+   button support, and most on-chip peripherals are not yet implemented.
+   Some of the values documented below (PLL/clock configuration, LED
+   polarity, JTAG IDCODE) were taken from TI's HALCoGen-generated reference
+   project or from the RM57L843 datasheet rather than confirmed against
+   this specific board's schematic — see the comments in
+   ``boards/arm/rm57/rm57l843-launchxl2/include/board.h`` for details.
+
+Features
+========
+
+* TI Hercules RM57L843 microcontroller
+* Dual-core lockstep ARM Cortex-R5F, running at 150 MHz HCLK (300 MHz
+  PLL/GCLK) in the current clock configuration
+* 4 MB of on-chip program flash, 512 KB of on-chip SRAM
+* Onboard XDS110 debug probe (JTAG)
+* 2 user LEDs
+* Single SCI (serial) interface currently supported
+
+.. note::
+
+   Peripherals that are part of the RM57L843 chip itself (N2HET, MibSPI,
+   CAN, ADC, the ESM diagnostic module, PBIST/STC self-test, etc.) but are
+   not yet wired up by this board port are tracked on the
+   :doc:`RM57 chip documentation page </platforms/arm/rm57/index>`.
+
+Buttons and LEDs
+================
+
+LEDs
+----
+
+The LAUNCHXL2-RM57L has two user LEDs, labeled **B6** and **B7** on the
+board silkscreen, driven by GIOB[6] and GIOB[7] respectively.
+
+Buttons
+-------
+
+Button support is not yet implemented by this board port.
+
+Pin Mapping
+===========
+
+Only the pins used by the currently supported peripherals are listed.
+
+.. list-table::
+   :widths: auto
+   :header-rows: 1
+
+   * - Pin
+     - Signal
+     - Notes
+   * - (n/a)
+     - LIN1RX / LIN1TX
+     - SCI1, used as the serial console
+   * - J2
+     - GIOB[6]
+     - User LED B6
+   * - F1
+     - GIOB[7]
+     - User LED B7
+
+.. note::
+
+   The RM57L843 SCI1/LIN1 pins are used at their reset-default (primary)
+   function, so no pin-mux configuration is required for the console.
+   Header/connector pin numbers for LIN1RX/LIN1TX have not been confirmed
+   against the LAUNCHXL2-RM57L schematic.
+
+Serial Console
+==============
+
+SCI1 is used as the serial console. The default configuration is:
+
+* 9600 baud, 8 data bits, no parity, 2 stop bits
+
+The baud rate and stop bits are configurable via ``CONFIG_SCI1_BAUD`` and
+``CONFIG_SCI1_2STOP``.
+
+Power Supply
+============
+
+The LAUNCHXL2-RM57L can be powered over USB through the onboard XDS110
+debug probe. Consult the
+`LAUNCHXL2-RM57L user's guide <https://www.ti.com/tool/LAUNCHXL2-RM57L>`_
+for the full range of supported input voltages.
+
+Debugging
+=========
+
+The board's onboard XDS110 probe exposes a JTAG interface (Hercules'
+ICEpick-C JTAG router is JTAG-only; XDS110's default SWD mode is not
+usable here). OpenOCD can be used with a Cortex-R5 (``cortex_r4`` driver)
+target configuration that routes through the ICEpick-C, followed by GDB
+to load and debug the image.
+
+nsh
+---
+
+Basic NuttShell configuration (console enabled on SCI1, at 9600 baud).

Documentation/platforms/arm/rm57/index.rst

@@ -0,0 +1,46 @@
+================
+TI/Hercules RM57
+================
+
+.. tags:: chip:rm57, arch:armv7-r
+
+The RM57 is part of TI's Hercules family of ARM Cortex-R5F safety
+microcontrollers, aimed at applications that need lockstep execution and
+built-in self-test (industrial, medical, and automotive safety systems).
+NuttX currently supports the **RM57L843** part.
+
+.. warning::
+
+   Support for this chip family is new and experimental. Only the SCI
+   (serial) and GIO (LED) peripherals have been brought up so far; the
+   PLL/clock configuration values, JTAG IDCODE, and LED polarity have not
+   all been independently confirmed against hardware/schematics. See the
+   :doc:`board documentation <boards/rm57l843-launchxl2/index>` for
+   details.
+
+Peripheral Support
+==================
+
+The following list indicates RM57 peripherals currently supported in NuttX:
+
+============== =====
+Peripheral     Notes
+============== =====
+SCI            Serial Communication Interface, used for the console
+GIO            General purpose I/O, used for LEDs
+============== =====
+
+.. todo::
+
+   Many peripherals available on the RM57L843 (N2HET, MibSPI, CAN, ADC,
+   the ESM diagnostic module, PBIST/STC self-test, etc.) are not yet
+   implemented. Contributions are welcome.
+
+Supported Boards
+=================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*

arch/arm/Kconfig

@@ -783,6 +783,15 @@ config ARCH_CHIP_TMS570
 	---help---
 		TI TMS570 family
 
+config ARCH_CHIP_RM57
+	bool "TI Hercules RM57"
+	select ARCH_HAVE_LOWVECTORS
+	select ARCH_HAVE_FETCHADD
+	select ARMV7R_MEMINIT
+	select ARMV7R_HAVE_DECODEFIQ
+	---help--- 
+		TI Hercules RM57 family (ARM Cortex-R5F)
+
 config ARCH_CHIP_TIVA
 	bool "TI Tiva"
 	select ARCH_HAVE_MPU
@@ -1360,6 +1369,7 @@ config ARCH_CHIP
 	default "stm32wl5"	if ARCH_CHIP_STM32WL5
 	default "str71x"	if ARCH_CHIP_STR71X
 	default "tms570"	if ARCH_CHIP_TMS570
+	default "rm57"		if ARCH_CHIP_RM57
 	default "xmc4"		if ARCH_CHIP_XMC4
 	default "mx8mp"		if ARCH_CHIP_MX8MP
 	default "cxd56xx"	if ARCH_CHIP_CXD56XX
@@ -1917,6 +1927,9 @@ endif
 if ARCH_CHIP_TMS570
 source "arch/arm/src/tms570/Kconfig"
 endif
+if ARCH_CHIP_RM57
+source "arch/arm/src/rm57/Kconfig"
+endif
 if ARCH_CHIP_XMC4
 source "arch/arm/src/xmc4/Kconfig"
 endif

arch/arm/include/rm57/chip.h

@@ -0,0 +1,66 @@
+/****************************************************************************
+ * arch/arm/include/rm57/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_RM57_CHIP_H
+#define __ARCH_ARM_INCLUDE_RM57_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Values below are taken from TI's HALCoGen project for RM57L843
+ * (HL_sys_link.ld for flash/RAM size, RM57L_Contents.dil VIM channel
+ * table for peripheral counts - see rm57l843_irq.h).
+ */
+
+#if defined(CONFIG_ARCH_CHIP_RM57L843)
+#  undef  RM57_CORTEX_R4                  /* Not Cortex-R4 family */
+#  undef  RM57_CORTEX_R4F                 /* Not Cortex-R4F family */
+#  undef  RM57_CORTEX_R5                  /* Not Cortex-R5 family */
+#  define RM57_CORTEX_R5F    1            /* Cortex-R5F family */
+
+/* 4MB Program FLASH (HL_sys_link.ld) */
+#  define RM57_PFLASH (4096*1024)
+#  define RM57_SRAM          (512*1024)   /* 512KB SRAM (HL_sys_link.ld) */
+
+/* DCAN1-4 (VIM req 16/29, 35/42, 45/55, 113/117) */
+#  define RM57_NCAN 4
+
+/* SCI1(LIN1)/SCI2/SCI3/SCI4 (HL_reg_sci.h) */
+#  define RM57_NSCI 4
+
+/* MibSPI1-5 (VIM req 12/26, 30, 37/38, 49/54, 53/56) */
+#  define RM57_NMIBSPI 5
+
+/* GIO Port A, Port B (HL_reg_gio.h) */
+#  define RM57_NGIOPORT 2
+#else
+#  error Unrecognized RM57 chip
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_RM57_CHIP_H */

arch/arm/include/rm57/irq.h

@@ -0,0 +1,91 @@
+/****************************************************************************
+ * arch/arm/include/rm57/irq.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_RM57_IRQ_H
+#define __ARCH_ARM_INCLUDE_RM57_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/rm57/chip.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* The VIM interrupt vector table has one phantom vector plus a set of
+ * real interrupt channels, per the classic Hercules VIM layout (see
+ * arch/arm/include/tms570/irq.h for the sibling family's equivalent).
+ */
+
+#define RM57_VECT_PHANTOM    0  /* The first is the "phantom" interrupt */
+
+/* Default channel assignments are MCU-dependent */
+
+#if defined(CONFIG_ARCH_CHIP_RM57L843)
+#  include <arch/rm57/rm57l843_irq.h>
+#else
+#  error "Unrecognized Hercules RM57 chip"
+#endif
+
+/* Total number of IRQ numbers.
+ * Includes all channels plus GIO second-level interrupts (if enabled).
+ * Excludes the phantom vector.  Zero corresponds to channel 0, vector 1.
+ */
+
+#define NR_IRQS  (RM57_IRQ_NCHANNELS + RM57_NGIO_IRQS)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_RM57_IRQ_H */