drivers/mmcsd: fix eMMC bus width switch sequencing#19502
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xiaoxiang781216 merged 1 commit intoJul 23, 2026
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@13022591351 please rebase your patch to the last master which fix the ci break. |
Two sequencing problems in the MMC wide bus path break eMMC 4-bit operation on hosts that program the bus width in the SDIO widebus / clock callbacks (e.g. STM32H7): 1. The SWITCH command (CMD6) is issued before the host has switched to wide bus operation. When the card completes the switch while the host is still in 1-bit mode the switch never takes effect and every following data transfer times out. Switch the host to wide bus operation before issuing CMD6. 2. The transfer clock is selected only at the end of mmcsd_widebus(), so the whole switch sequence runs at ID-mode clock and, on the affected hosts, the final clock update does not take effect either, leaving the bus at ~400 kHz. Select the MMC transfer clock before calling mmcsd_widebus(), and pick CLOCK_MMC_TRANSFER_4BIT when wide bus operation is active (mirroring the SD card path) so a later clock selection cannot revert the host to 1-bit. No behavior change for SD cards, and no change on hosts whose widebus callback only records the requested state. Tested on a custom STM32H743 board with eMMC: sd_bench sequential write ~4.1 MB/s, sequential read ~6.3 MB/s (previously all data transfers timed out). Signed-off-by: DuoYuWang <thirteenking.wang@gmail.com>
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Summary
The MMC wide bus switch sequence breaks eMMC 4-bit operation on hosts
that program the bus width in the SDIO widebus/clock callbacks (e.g.
STM32H7): CMD6 is issued before the host switched to wide bus (the
switch silently fails and all following transfers time out), and the
transfer clock is only selected after the switch sequence (it never
takes effect, leaving the bus at ID-mode ~400 kHz).
Switch the host to wide bus before CMD6, select the MMC transfer clock
before calling mmcsd_widebus(), and use CLOCK_MMC_TRANSFER_4BIT when
wide bus operation is active (mirroring the SD path).
Impact
MMC/eMMC only. SD cards are unaffected; hosts whose widebus callback
only records state are unaffected.
Testing
Custom STM32H743 board with eMMC: sd_bench sequential write ~4.1 MB/s,
read ~6.3 MB/s (previously all data transfers timed out).