arch/mips/jz4780: Add USB host and display controller drivers

Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst

@@ -66,3 +66,10 @@ net
 
 The telnet daemon is included, so the CI20 board can be connected to through telnet.
 
+jumbo
+-----
+
+* Basic serial console access to the NSH shell.
+* Networking support through the RJ45 connector.
+* USB host support: mass storage, hub, keyboard and mouse.
+* Builtin Apps: dd, hidkbd, ping, tc, fb, nsh, sh, telnetd

arch/mips/include/jz4780/chip.h

@@ -67,27 +67,57 @@
 #define OSTCSR              (JZTMR_BASE + 0xec)
 
 #define TESR                (JZTMR_BASE + 0x14)
-
-#define TESR_OSTEN          (1 << 15)
-#define TESR_TCEN(n)        (1 << (n))
+#  define TESR_OSTEN        (1 << 15)
+#  define TESR_TCEN(n)      (1 << (n))
 
 #define TMSR                (JZTMR_BASE + 0x34)
 #define TMCR                (JZTMR_BASE + 0x38)
-#define TMCR_OSTMCL         (1 << 15)
-#define TMCR_FMCL5          (1 << 5)
-#define TMCR_FMCL(n)        (1 << (n))
+#  define TMCR_OSTMCL       (1 << 15)
+#  define TMCR_FMCL5        (1 << 5)
+#  define TMCR_FMCL(n)      (1 << (n))
 
 #define TFR                 (JZTMR_BASE + 0x20)
 
 #define TFCR                (JZTMR_BASE + 0x28)
-#define TFCR_OSTFCL         (1 << 15)
-#define TFCR_FFCL5          (1 << 5)
-#define TFCR_FFCL(n)        (1 << (n))
+#  define TFCR_OSTFCL       (1 << 15)
+#  define TFCR_FFCL5        (1 << 5)
+#  define TFCR_FFCL(n)      (1 << (n))
 
 #define TCNT(n)             (JZTMR_BASE + 0x48 + (n)*0x10)
 #define TCSR(n)             (JZTMR_BASE + 0x4C + (n)*0x10)
 #define TDFR(n)             (JZTMR_BASE + 0x40 + (n)*0x10)
 
+#define CLKGR0_REG          0xb0000020
+#  define CLKGR0_OTG0       (1 << 2)
+#  define CLKGR0_UHC        (1 << 24)
+#  define CLKGR0_LCD        (1 << 28)
+#  define CLKGR0_TVE        (1 << 27)
+
+#define OPCR_REG            0xb0000024
+#  define OPCR_SPENDN1      (1 << 6)
+
+#define CLKGR1_REG          0xb0000028
+#  define CLKGR1_HDMI       (1 << 9)
+
+#define USBPCR_REG          0xb000003c
+#  define USBPCR_POR        (1 << 22)
+
+#define USBPCR1_REG         0xb0000048
+#  define REFCLK_DIV_MSK    0xfcffffff  /* clears bits 25:24 */
+#  define REFCLK_DIV_48MHZ  0x02000000  /* bits 25:24 */
+#  define WORD_IF_16BIT     0x000c0000  /* bits 19:18 */
+
+#define LP1CDR_REG          0xb0000054
+#  define LPCDR_VAL         0x15
+#  define LPCS_VPLL         0X80000000
+#  define CE_LCD            (1 << 28)
+#  define LCD_BUSY          (1 << 27)
+
+#define HDMICDR_REG         0xb000008c
+
+#define SRBC_REG            0xb00000c4
+#  define SRBC_UHC_SR       (1 << 14)
+
 #define TICKS_PER_MS        (48000/16)
 
 #define CHIP_JZ4780         1

arch/mips/src/jz4780/Kconfig

@@ -4,4 +4,102 @@
 #
 
 if ARCH_CHIP_JZ4780
+comment "JZ4780 Configuration Options"
+
+menu "JZ4780 Peripheral Support"
+config JZ4780_LCD
+	bool "LCD controller"
+	default n
+
+config JZ4780_OHCI
+	bool "Full/low speed OHCI support"
+	default n
+	select SCHED_HPWORK
+	select USBHOST
+	select USBHOST_HAVE_ASYNCH
+	select USBHOST_ASYNCH
+	select USBHOST_WAITER
+	---help---
+		Build support for the JZ4780 USB full speed Open Host Controller
+		Interface (OHCI).
+
+
+if JZ4780_OHCI
+config JZ4780_OHCI_NEDS
+	int "Number of endpoint descriptors"
+	default 6
+
+config JZ4780_OHCI_NTDS
+	int "Number of transfer descriptors"
+	default 9
+
+config JZ4780_OHCI_TDBUFFERS
+	int "Number of transfer descriptor buffers"
+	default 6
+
+config JZ4780_OHCI_TDBUFSIZE
+	int "Size of one transfer descriptor buffer"
+	default 128
+	---help---
+		The size of one transfer descriptor (TD) buffer in bytes.  The TD
+		buffer size must be an even number of 32-bit words
+
+config JZ4780_OHCI_REGDEBUG
+	bool "Enable low-level OHCI register debug"
+	default n
+	depends on DEBUG_USB_INFO
+
+endif # JZ4780_OHCI
+
+config JZ4780_EHCI
+	bool "High speed EHCI support"
+	default n
+	select USBHOST
+	select USBHOST_HAVE_ASYNCH
+	select USBHOST_WAITER
+	---help---
+		Build support for the JZ4780 USB high speed Enhanced Host Controller
+		Interface (EHCI).  If low/full speed is needed too, then you must
+		also enable the OHCI controller.
+
+if JZ4780_EHCI
+
+config JZ4780_EHCI_NQHS
+	int "Number of Queue Head (QH) structures"
+	default 8
+	---help---
+		Configurable number of Queue Head (QH) structures.  The default is
+		one per Root hub port plus one for EP0 (4).
+
+config JZ4780_EHCI_NQTDS
+	int "Number of Queue Element Transfer Descriptor (qTDs)"
+	default 10
+	---help---
+		Configurable number of Queue Element Transfer Descriptor (qTDs).
+		The default is one per root hub plus three from EP0 (6).
+
+config JZ4780_EHCI_BUFSIZE
+	int "Size of one request/descriptor buffer"
+	default 1024
+	---help---
+		The size of one request/descriptor buffer in bytes.  The TD buffe
+		size must be an even number of 32-bit words and must be large enough
+		to hangle the largest transfer via a SETUP request.
+
+config JZ4780_EHCI_PREALLOCATE
+	bool "Preallocate descriptor pool"
+	default y
+	---help---
+		Select this option to pre-allocate EHCI queue and descriptor
+		structure pools in .bss.  Otherwise, these pools will be
+		dynamically allocated using kmm_memalign().
+
+config JZ4780_EHCI_REGDEBUG
+	bool "Enable low-level EHCI register debug"
+	default n
+	depends on DEBUG_USB_INFO
+
+endif # JZ4780_EHCI
+endmenu # JZ4780 Peripheral Support
+
 endif

arch/mips/src/jz4780/Make.defs

@@ -51,3 +51,21 @@ endif
 CHIP_CSRCS  = jz4780_lowinit.c jz4780_exception.c jz4780_decodeirq.c
 CHIP_CSRCS += jz4780_irq.c jz4780_timerisr.c jz4780_gpio.c
 CHIP_CSRCS += jz4780_cache.c
+
+ifeq ($(CONFIG_USBHOST),y)
+CHIP_CSRCS += jz_usbhost.c
+
+ifeq ($(CONFIG_JZ4780_OHCI),y)
+CHIP_CSRCS += jz4780_ohci.c
+endif
+
+ifeq ($(CONFIG_JZ4780_EHCI),y)
+CHIP_CSRCS += jz4780_ehci.c
+endif
+endif
+
+ifeq ($(CONFIG_ALLOW_BSD_COMPONENTS),y)
+ifeq ($(CONFIG_JZ4780_LCD),y)
+CHIP_CSRCS += jz4780_lcd.c
+endif
+endif