Computer Organization Project 2: ARM Single-Cycle Processor

Authors: Nathan A. & Devin Nowowiejski
Date: October 2025

Overview

This project implements a single-cycle ARM processor with memory-mapped I/O capabilities on the Intel DE10-Lite FPGA board. The design includes a complete datapath, control unit, memory subsystem, and interactive debugging/display interface.

Features

• Single-Cycle ARM Processor: Implements a subset of ARMv4 instructions
• Memory-Mapped I/O: Two configurable I/O ports (Port 0 and Port 1) with data and control registers
• Interactive Debugging: PeekTop display system for real-time processor state visualization
• Debounced Step Clock: Manual clock stepping for instruction-by-instruction execution
• Seven-Segment Display: Hexadecimal display output for debugging and I/O visualization

Hardware Requirements

• Intel DE10-Lite FPGA Development Board (MAX 10)
• Quartus Prime software for synthesis and programming

Project Structure

Top-Level Modules

• SLP.sv: Top-level integration module connecting all components
  • Instantiates CPU, memories, debouncer, and PeekTop display
  • Maps FPGA inputs (keys, switches, clock) to outputs (seven-segment displays)

Processor Core

• arm.sv: ARM processor coordinator

  • Coordinates instruction decoding, execution, and memory access
  • Integrates control unit and datapath

• datapath.sv: Processor datapath

  • Implements register file, ALU, multiplexers, and data flow paths
  • Provides debug signals for state visualization

• ControlUnit.sv: Instruction decoder and control signal generator

  • Decodes instruction opcodes and condition codes
  • Generates control signals for datapath components

• ALU.sv: Arithmetic Logic Unit

  • Performs arithmetic and logical operations
  • Updates condition flags (N, Z, C, V)

Memory Components

• imem.sv: Instruction memory (ROM)

  • Reads 32-bit instructions from memfile.dat
  • Word-aligned access (256 instructions capacity)

• MemoryWithIO.sv: Data memory with memory-mapped I/O

  • 1024-word RAM for data storage
  • Two configurable I/O ports with data and control registers
  • Memory-mapped addresses for I/O operations

Supporting Modules

• Register_File.sv: 16-register file (R0-R15)

  • Dual read ports, single write port
  • Includes program counter (R15) support

• PCPlus4.sv: Program counter incrementer

• Extlmm.sv: Immediate value extender

• flopr.sv: Flip-flop with reset

• mux_n.sv: Parameterized n-bit multiplexer

Debug and Display

• PeekTop.sv: Interactive debugging interface

  • Display modes: PC, Instruction, Register contents, ALU signals, Memory I/O
  • Input mode: Manually override I/O port inputs using switches
  • Step-through execution with visual feedback

• debouncer.sv: Key debouncing module

  • Provides clean clock/button signals from mechanical switches

• SevenSegHex.sv: Seven-segment display decoder

  • Converts 4-bit hex values to seven-segment patterns

Memory Map

Data Memory (MemoryWithIO)

• 0x00000000 - 0x00000FFF: RAM (1024 words)
• 0x00001000: Port 0 Data Register
• 0x00001004: Port 0 Control Register (bit 0: 1=output, 0=input)
• 0x00001008: Port 1 Data Register
• 0x0000100C: Port 1 Control Register (bit 0: 1=output, 0=input)

FPGA Pin Mapping

Inputs

• KEY0: Step clock (debounced, active-low)
• KEY1: Peek button (display current PC when pressed)
• SW[9:0]: Slide switches for mode selection and data input
  • SW9: Display mode selection (see PeekTop modes)
  • SW8: Input mode override
  • SW[7:0]: Data input for I/O override / display selection

Outputs

• HEX5-HEX0: Six seven-segment displays showing hexadecimal values

Usage

Programming the FPGA

1. Open SLP.qpf in Quartus Prime
2. Compile the design (Processing → Start Compilation)
3. Program the FPGA (Tools → Programmer)

Loading Instructions

1. Create or modify memfile.dat with ARM machine code (hexadecimal format)
2. Recompile the design to update instruction memory
3. Program the FPGA

Operating the Processor

1. Step Clock (KEY0): Press to execute one instruction
2. Peek Button (KEY1): Hold to display current PC value
3. Mode Selection (SW9): Choose display mode
4. I/O Override (SW8): Set to 1 for manual I/O input mode

Display Modes (via SW9 and PeekTop)

The system supports multiple visualization modes for debugging:

• Program Counter (PC)
• Current Instruction
• Register file contents (selected via switches)
• ALU operands and results
• Memory I/O port registers
• Output port values

Development Notes

Design Methodology

Based on the single-cycle processor architecture from Digital Design and Computer Architecture by Harris & Harris (Chapter 7).

Key Design Decisions

1. Single-cycle execution: Each instruction completes in one clock cycle
2. Manual stepping: Debounced button press drives clock for educational purposes
3. Memory-mapped I/O: Unified address space for memory and I/O operations
4. Peek interface: Non-intrusive debugging without modifying processor state

Testing

The project includes:

• expected_peek_with_io.csv: Expected output values for verification
• Test programs in memfile.dat format

Files

Primary Source Files

• SLP.sv (Top-level)
• arm.sv, datapath.sv, ControlUnit.sv
• ALU.sv, Register_File.sv
• imem.sv, MemoryWithIO.sv
• PeekTop.sv, debouncer.sv, SevenSegHex.sv

Quartus Project Files

• SLP.qpf, SLP.qsf (Project configuration)
• SLP.sdc (Timing constraints)

Build Artifacts

• db/ - Database files
• incremental_db/ - Incremental compilation data
• output_files/ - Programming files and reports

Known Issues

Backup files (*.bak) are preserved for reference but not used in compilation.

References

• Harris, S. L., & Harris, D. M. Digital Design and Computer Architecture: ARM Edition
  • HDL Example 7.1 (Single Cycle Processor, page 411)
  • HDL Example 7.15 (Instruction Memory, page 427)

License

Educational project for Computer Organization coursework.