Open
Conversation
Replace unconditional enabling of caches with runtime detection and enabling only on devices that may have it based on the base architecture version. Add data cache invalidation. Make runtime check for MPU disabling. Known good implementation of cache management is in CMSIS https://github.com/ARM-software/CMSIS_6/blob/main/CMSIS/Core/Include/m-profile/armv7m_cachel1.h However it uses pre-computed parameters for bit manipulation. References to relevant system registers: * ICIALLU: https://developer.arm.com/documentation/ddi0601/2025-12/AArch32-Instructions/ICIALLU--Instruction-Cache-Invalidate-All-to-PoU?lang=en * CLIDR: https://developer.arm.com/documentation/ddi0601/2025-12/AArch32-Registers/CLIDR--Cache-Level-ID-Register?lang=en * CSSELR: https://developer.arm.com/documentation/ddi0601/2025-12/AArch32-Registers/CSSELR--Cache-Size-Selection-Register?lang=en * CCSIDR: https://developer.arm.com/documentation/ddi0601/2025-12/AArch32-Registers/CCSIDR--Current-Cache-Size-ID-Register?lang=en * DCISW: https://developer.arm.com/documentation/ddi0601/2025-12/AArch32-Instructions/DCISW--Data-Cache-line-Invalidate-by-Set-Way * MPU_TYPE: https://developer.arm.com/documentation/ddi0419/c/System-Level-Architecture/System-Address-Map/Protected-Memory-System-Architecture--PMSAv6/MPU-Type-Register--MPU-TYPE Tested with the FVP and by comparing generated bit patterns against simulated CMSIS run.
vhscampos
reviewed
Mar 9, 2026
|
|
||
| #if BOOTCODE_M_ARCH_CACHE_SUPPORTED | ||
| static inline void sync_barriers() { | ||
| static constexpr unsigned int FullSystemScope = 0xf; |
Contributor
There was a problem hiding this comment.
I don't think static constexpr makes any difference here. Unless I'm missing something, I suggest you change it to const unsigned int.
Contributor
Author
There was a problem hiding this comment.
static would not make a difference, agreed, I will remove, constexpr I expect to ensure this is compile time only (which it probably would be in this trivial case anyway - just to express the intent).
Contributor
Author
There was a problem hiding this comment.
Removed the static here.
vhscampos
approved these changes
Mar 12, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Replace unconditional enabling of caches with runtime detection and enabling only on devices that may have it based on the base architecture version. Add data cache invalidation.
Make runtime check for MPU disabling.
Known good implementation of cache management is in CMSIS https://github.com/ARM-software/CMSIS_6/blob/main/CMSIS/Core/Include/m-profile/armv7m_cachel1.h However it uses pre-computed parameters for bit manipulation.
References to relevant system registers:
Tested with the FVP and by comparing generated bit patterns against simulated CMSIS run.