atomic_v7: add memory barriers to atomic bit RMW#808
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The bitwise ldrex/strex RMW had no barriers, so a later load could be reordered ahead of the atomic write (e.g. signal.c sets tc_SigRecvd then reads tc_State). Bracket the loop with dmb and add the memory clobber to give the operation sequential-consistency ordering.
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The bitwise ldrex/strex RMW had no barriers, so a later load could be reordered ahead of the atomic write (e.g. signal.c sets tc_SigRecvd then reads tc_State). Bracket the loop with dmb and add the memory clobber to give the operation sequential-consistency ordering.