creatorsim · dcamarmas · Mar 27, 2026 · Mar 23, 2026 · Mar 23, 2026 · Mar 27, 2026
diff --git a/examples/RISCV-32-Sail-Validation/list.json b/examples/RISCV-32-Sail-Validation/list.json
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf b/examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf b/examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf b/examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf b/examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf b/examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf b/examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf b/examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-div.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-div.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf
diff --git a/examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf b/examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf
diff --git a/examples/RISCV-64-Sail-Validation/list.json b/examples/RISCV-64-Sail-Validation/list.json
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf b/examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf b/examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf b/examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf b/examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf b/examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf b/examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srai.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraiw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sraw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srl.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srli.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srliw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-srlw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sub.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-subw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-sw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-xor.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf b/examples/RISCV-64-Sail-Validation/rv64ui-p-xori.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-div.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-div.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divuw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-divw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mul.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulh.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhsu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulhu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-mulw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-rem.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remu.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remuw.elf
diff --git a/examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf b/examples/RISCV-64-Sail-Validation/rv64um-p-remw.elf
diff --git a/src/core/events.mts b/src/core/events.mts
@@ -39,6 +39,7 @@ export const CoreEventTypes = {
     ARDUINO_PIN_CHANGED: "arduino-pin-write",
     ARDUINO_RESET: "arduino-reset",
     ARDUINO_PIN_INTERRUPT: "arduino-pin-interrupt",
+    VALIDATION_UPDATE: "update-validation",
 } as const;
 
 /**

diff --git a/src/core/executor/sailSimRV/sailExecutor.mjs b/src/core/executor/sailSimRV/sailExecutor.mjs
@@ -3,7 +3,150 @@
 import sail64sim from "./wasm/riscv_sim_RV64.js"
 import sail32vdsim from "./wasm/riscv_sim_RV32vd.js"
 import { vectoren, doubleen } from "../../assembler/sailAssembler/web/CNAssambler.mjs";
+import { coreEvents } from "../../events.mts";
+
 export var sailexec;
+var programs = [];
+
+async function cargarProgramas32(jsonPath) {
+
+  const response = await fetch(jsonPath);
+  const lista = await response.json();
+
+  const programas = await Promise.all(
+    lista.map(async entry => {
+
+      const binResponse = await fetch(entry.url);
+      const buffer = await binResponse.arrayBuffer();
+
+      const programa = {
+        name: entry.name,
+        binary: new Uint8Array(buffer)
+      };
+
+      if ("doubleen" in entry) programa.doubleen = entry.doubleen;
+      if ("vectoren" in entry) programa.vectoren = entry.vectoren;
+
+      return programa;
+    })
+  );
+
+  return programas;
+}
+
+async function cargarProgramas64(jsonPath){
+
+  const response = await fetch(jsonPath);
+  const lista = await response.json();
+
+  const programas = await Promise.all(
+    lista.map(async entry => {
+
+      const binResponse = await fetch(entry.url);
+      const buffer = await binResponse.arrayBuffer();
+
+      const programa = {
+        name: entry.name,
+        binary: new Uint8Array(buffer)
+      };
+
+      return programa;
+    })
+  );
+
+  return programas;
+}
+
+export async function SailTest32(){
+    // Reset de las variables test
+    document.app.$data.passed_test          = 0;
+    document.app.$data.failed_test          = 0;
+    document.app.$data.testing              = true;
+    document.app.$data.c_kernel             = false;
+    if (programs.length === 0)
+        programs = await cargarProgramas32("../../../../examples/RISCV-32-Sail-Validation/list.json");
+
+    for (let index = 0; index < programs.length; index++) {
+
+        document.app.$data.execution_mode_run   = -1;
+        const element = programs[index];
+        let depsLeft = Infinity;
+        if (element.vectoren && element.doubleen) {
+            sailexec = await sail32vdsim({
+                noInitialRun: true,
+                // print: (t) => console.log('[sim32]', t),
+                // printErr: (t) => console.warn('[sim32:err]', t),
+                // onAbort: (t) => console.error("[sim32:abort]", t),
+                monitorRunDependencies(left) {
+                    depsLeft = left;
+                    console.log("[sim32] deps pending:", left);
+                },
+            });
+        } else {
+            sailexec = await sail32sim({
+                noInitialRun: true,
+                // print: (t) => console.log('[sim32]', t),
+                // printErr: (t) => console.warn('[sim32:err]', t),
+                // onAbort: (t) => console.error("[sim32:abort]", t),
+                monitorRunDependencies(left) {
+                    depsLeft = left;
+                    console.log("[sim32] deps pending:", left);
+                },
+            });
+        }
+
+        await new Promise((resolve) => {
+            const check = () => {
+                if (depsLeft === 0) resolve();
+                else setTimeout(check, 100);
+            };
+            check();
+        });
+        document.app.$data.execution_mode_run = 0;
+        sailexec.run([element.binary, "--entry-address", "0x80000000", "--cache-pol", "1", "-p", "output.elf"]);
+        coreEvents.emit("update-validation");
+
+
+    }
+
+    document.app.$data.testing = false;
+
+}
+export async function SailTest64(){
+    var filed_tests = [];
+    document.app.$data.passed_test          = 0;
+    document.app.$data.failed_test          = 0;
+    document.app.$data.testing              = true;
+    document.app.$data.c_kernel             = false;
+    if (programs.length === 0)
+        programs = await cargarProgramas64("../../../../examples/RISCV-64-Sail-Validation/list.json");
+
+    for (let index = 0; index < programs.length; index++) {
+
+        document.app.$data.execution_mode_run   = -1;
+        const element = programs[index];
+        let depsLeft = Infinity;
+        sailexec = await sail64sim({
+            noInitialRun: true,
+            monitorRunDependencies(left) {
+                depsLeft = left;
+                console.log("[sim64] deps pending:", left);
+            },
+        });
+        await new Promise((resolve) => {
+            const check = () => {
+                if (depsLeft === 0) resolve();
+                else setTimeout(check, 100);
+            };
+            check();
+        });
+        document.app.$data.execution_mode_run = 0;
+        sailexec.run([element.binary, "--entry-address", "0x80000000", "--cache-pol", "1", "-p", "output.elf"]);
+        coreEvents.emit("update-validation");
+    }
+
+    document.app.$data.testing = false;
+}
 export async function SailExecute(binary, flags){
     let depsLeft = Infinity;
     if (architecture.config.name === "SRV32") {
@@ -64,7 +207,6 @@
     // Once it is initialized, lets run the program
 
     // document.app.$data.execution_mode_run = 0;
-    console.log(flags);
 
     sailexec.run([binary, ...flags]);
 

diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js
@@ -16,7 +16,7 @@ var Module = (() => {
   var insn_number;
 
   return function (Module) {
-    document.app.$data.is_breakpoint = instructions[0].Break;
+    document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
     var pc_sail = crex_findReg_bytag("program_counter");
     var pc_min = architecture.memory_layout.text.start;
     var pc_max = architecture.memory_layout.text.end;
@@ -1194,8 +1194,7 @@ var Module = (() => {
       console.warn(message);
     }
 
-    var out = Module["print"] /*|| console.log.bind(console)*/;
-    // var out = console.log.bind(console);
+    var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"];
     var err = Module["printErr"] /*|| console.warn.bind(console)*/;
 
     Object.assign(Module, moduleOverrides);
@@ -7824,27 +7823,33 @@ var Module = (() => {
       }
       if (keepRuntimeAlive()) {
         if (!implicit) {
-
-          for (let i = 0; i < instructions.length; i++){
-            instructions[i]._rowVariant = '';
-          }
-          status.run_program = -1; // program finished
-          if (statusw !== 0){
-            coreEvents.emit("executor-buttons-update", {
-              reset_disable: false,
-              instruction_disable: true,
-              run_disable: true,
-              stop_disable: false,
-            });
-            show_notification("Your program has finished with errors.", "danger");
+          if (!document.app.$data.testing) {
+            for (let i = 0; i < instructions.length; i++){
+              instructions[i]._rowVariant = '';
+            }
+            status.run_program = -1; // program finished
+            if (statusw !== 0){
+              coreEvents.emit("executor-buttons-update", {
+                reset_disable: false,
+                instruction_disable: true,
+                run_disable: true,
+                stop_disable: false,
+              });
+              show_notification("Your program has finished with errors.", "danger");
+            } else {
+              coreEvents.emit("executor-buttons-update", {
+                reset_disable: false,
+                instruction_disable: false,
+                run_disable: false,
+                stop_disable: true,
+                isFinished: true,
+              });
+            }
           } else {
-            coreEvents.emit("executor-buttons-update", {
-              reset_disable: false,
-              instruction_disable: false,
-              run_disable: false,
-              stop_disable: true,
-              isFinished: true,
-            });
+            if (statusw === 0)
+              document.app.$data.passed_test += 1;
+            else 
+              document.app.$data.failed_test += 1;
           }
           var msg =
             "program exited (with status: " +

diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.js
@@ -16,7 +16,8 @@ var Module = (() => {
   var _scriptName = import.meta.url;
   var insn_number;
 
-  return async function (moduleArg = {}) {document.app.$data.is_breakpoint = instructions[0].Break;
+  return async function (moduleArg = {}) {
+    document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
     var pc_sail = crex_findReg_bytag("program_counter");
     var pc_min = architecture.memory_layout.text.start;
     var pc_max = architecture.memory_layout.text.end;
@@ -957,8 +958,7 @@ var Module = (() => {
       console.warn(message);
     }
 
-    var out = Module["print"] /*|| console.log.bind(console)*/;
-    // var out = console.log.bind(console);
+    var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"]; 
     var err = Module["printErr"] /*|| console.warn.bind(console)*/;
 
 
@@ -4290,26 +4290,33 @@ var Module = (() => {
       EXITSTATUS = statusw;
       checkUnflushedContent();
       if (keepRuntimeAlive() && !implicit) {
-        for (let i = 0; i < instructions.length; i++){
-          instructions[i]._rowVariant = '';
-        }
-        status.run_program = -1; // program finished
-        if (statusw !== 0){
-          coreEvents.emit("executor-buttons-update", {
-            reset_disable: false,
-            instruction_disable: true,
-            run_disable: true,
-            stop_disable: false,
-          });
-          show_notification("Your program has finished with errors.", "danger");
+        if (!document.app.$data.testing){
+          for (let i = 0; i < instructions.length; i++){
+            instructions[i]._rowVariant = '';
+          }
+          status.run_program = -1; // program finished
+          if (statusw !== 0){
+            coreEvents.emit("executor-buttons-update", {
+              reset_disable: false,
+              instruction_disable: true,
+              run_disable: true,
+              stop_disable: false,
+            });
+            show_notification("Your program has finished with errors.", "danger");
+          } else {
+            coreEvents.emit("executor-buttons-update", {
+              reset_disable: false,
+              instruction_disable: false,
+              run_disable: false,
+              stop_disable: true,
+              isFinished: true,
+            });
+          }
         } else {
-          coreEvents.emit("executor-buttons-update", {
-            reset_disable: false,
-            instruction_disable: false,
-            run_disable: false,
-            stop_disable: true,
-            isFinished: true,
-          });
+          if (statusw === 0)
+            document.app.$data.passed_test += 1;
+          else 
+            document.app.$data.failed_test += 1;
         }
         var msg = `program exited (with status: ${statusw}), but keepRuntimeAlive() is set (counter=${runtimeKeepaliveCounter}) due to an async operation, so halting execution but not exiting the runtime or preventing further async execution (you can use emscripten_force_exit, if you want to force a true shutdown)`;
         readyPromiseReject(msg);

diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV32vd.wasm
diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.js
@@ -16,7 +16,7 @@ var Module = (() => {
   var insn_number;
 
   return async function (moduleArg = {}) {
-    document.app.$data.is_breakpoint = instructions[0].Break;
+    document.app.$data.is_breakpoint = (instructions.length !== 0) ? instructions[0].Break : false;
     var pc_sail = crex_findReg_bytag("program_counter");
     var pc_min = architecture.memory_layout.text.start;
     var pc_max = architecture.memory_layout.text.end;
@@ -1009,7 +1009,7 @@ var Module = (() => {
     }
 
 
-    var out = Module["print"] /*|| console.log.bind(console)*/;
+    var out = (document.app.$data.testing === true ) ? console.log.bind(console) : Module["print"];
     var err = Module["printErr"] /*|| console.error.bind(console)*/;
 
 
@@ -4341,27 +4341,33 @@ var Module = (() => {
       EXITSTATUS = statusw;
       checkUnflushedContent();
       if (keepRuntimeAlive() && !implicit) {
-
-        for (let i = 0; i < instructions.length; i++){
-          instructions[i]._rowVariant = '';
-        }
-        status.run_program = -1; // program finished
-        if (statusw !== 0){
-          coreEvents.emit("executor-buttons-update", {
-            reset_disable: false,
-            instruction_disable: true,
-            run_disable: true,
-            stop_disable: false,
-          });
-          show_notification("Your program has finished with errors.", "danger");
+        if (!document.app.$data.testing) {
+          for (let i = 0; i < instructions.length; i++){
+            instructions[i]._rowVariant = '';
+          }
+          status.run_program = -1; // program finished
+          if (statusw !== 0){
+            coreEvents.emit("executor-buttons-update", {
+              reset_disable: false,
+              instruction_disable: true,
+              run_disable: true,
+              stop_disable: false,
+            });
+            show_notification("Your program has finished with errors.", "danger");
+          } else {
+            coreEvents.emit("executor-buttons-update", {
+              reset_disable: false,
+              instruction_disable: false,
+              run_disable: false,
+              stop_disable: true,
+              isFinished: true,
+            });
+          }
         } else {
-          coreEvents.emit("executor-buttons-update", {
-            reset_disable: false,
-            instruction_disable: false,
-            run_disable: false,
-            stop_disable: true,
-            isFinished: true,
-          });
+          if (statusw === 0)
+            document.app.$data.passed_test += 1;
+          else 
+            document.app.$data.failed_test += 1;
         }
         var msg = `program exited (with status: ${statusw}), but keepRuntimeAlive() is set (counter=${runtimeKeepaliveCounter}) due to an async operation, so halting execution but not exiting the runtime or preventing further async execution (you can use emscripten_force_exit, if you want to force a true shutdown)`;
         readyPromiseReject(msg);

diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm b/src/core/executor/sailSimRV/wasm/riscv_sim_RV64.wasm
diff --git a/src/web/App.vue b/src/web/App.vue
@@ -354,6 +354,14 @@ export default {
       target_port: "",
       target_location: "~/creator",
       flash_url: "http://localhost:8080",
+
+      /* Validation test */
+      // Stats
+      passed_test: 0,
+      failed_test: 0,
+
+      // Check testing execution
+      testing: false,
     };
   },