google traces gem5 (v1)

README

@@ -1,3 +1,30 @@
+## Analyzing Google Traces in gem5
+
+This branch contains necessary code and scripts to run google workload traces with
+gem5. These changes will eventually move to the mainline gem5 repo.
+
+Follow the following steps to run google traces with gem5:
+
+Compile gem5.
+
+Download Google Workload Traces from [here](https://dynamorio.org/google_workload_traces.html).
+
+In the current folder there are two example scripts that can be used to run google traces.
+
+- [drtrace.py](./drtrace.py): This is a normal python script that imports all gem5 objects to manually set up a target system to simulate. `DRTraceReader` and `DRTracePlayer` are the trace reader and player objects that are used in this script. Example command:
+
+```sh
+build/X86/gem5.opt drtrace.py --path <path of folder containing all traces> --workload <benchmark_name, options: charlie, delta, merced, whiskey> --players <number of trace players to use> --dram <DRAM device to use, options:ddr4_2400, hbm_2000, ddr5_8400>
+```
+
+- [drtrace-stdlib.py](./drtrace-stdlib.py): This script uses gem5 standard library components to set-up a system to simulate. `DRTracePlayerGenerator` is the standard library component that creates a trace reader/player system. The arguments this class accepts include: `num_cores` `max_ipc`, and `max_outstanding_reqs`. Example command:
+
+```sh
+build/X86/gem5.opt drtrace-stdlib.py --path <path of folder containing all traces> --workload <benchmark_name, options: charlie, delta, merced, whiskey> --players <number of trace players to use>  --ruby <Use classic or ruby caches, options: 0,1>
+```
+
+## Default gem5 README
+
 This is the gem5 simulator.
 
 The main website can be found at http://www.gem5.org

dr_trace_player.py

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+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+from typing import Optional
+from pathlib import Path
+
+from m5.objects import DRTraceReader
+from gem5.utils.override import overrides
+
+from gem5.components.processors.abstract_generator import AbstractGenerator
+from gem5.components.boards.abstract_board import AbstractBoard
+from dr_trace_player_core import DRTracePlayerCore
+
+
+class DRTracePlayerGenerator(AbstractGenerator):
+    def __init__(
+        self,
+        trace_directory: Path,
+        num_cores: int,
+        max_ipc: int,
+        max_outstanding_reqs: int,
+        clk_freq: Optional[str] = None,
+    ):
+        super().__init__(
+            cores=[
+                DRTracePlayerCore(
+                    max_ipc=max_ipc,
+                    max_outstanding_reqs=max_outstanding_reqs,
+                    clk_freq=clk_freq,
+                )
+                for _ in range(num_cores)
+            ]
+        )
+
+        self.reader = DRTraceReader(
+            directory=trace_directory, num_players=num_cores
+        )
+
+        for core in self.get_cores():
+            core.set_reader(self.reader)
+
+    @overrides(AbstractGenerator)
+    def start_traffic(self):
+        """
+        Since DRTracePlayer does not need a call to start_traffic to
+        start generation. This function is just pass.
+        """
+        pass
+
+    @overrides(AbstractGenerator)
+    def incorporate_processor(self, board: AbstractBoard) -> None:
+        super().incorporate_processor(board)
+        for core in self.get_cores():
+            core.set_memory_range(board.mem_ranges[0])

dr_trace_player_core.py

@@ -0,0 +1,72 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from typing import Optional
+
+from gem5.components.processors.abstract_generator_core import (
+    AbstractGeneratorCore,
+)
+from gem5.components.processors.abstract_core import AbstractCore
+from gem5.utils.override import overrides
+
+from m5.objects import (
+    AddrRange,
+    DRTracePlayer,
+    DRTraceReader,
+    Port,
+    SrcClockDomain,
+    VoltageDomain,
+)
+
+
+class DRTracePlayerCore(AbstractGeneratorCore):
+    def __init__(
+        self,
+        max_ipc: int,
+        max_outstanding_reqs: int,
+        clk_freq: Optional[str] = None,
+    ):
+        super().__init__()
+        self.player = DRTracePlayer(
+            max_ipc=max_ipc,
+            max_outstanding_reqs=max_outstanding_reqs,
+            send_data=True,
+        )
+        if clk_freq:
+            clock_domain = SrcClockDomain(
+                clock=clk_freq, voltage_domain=VoltageDomain()
+            )
+            self.generator.clk_domain = clock_domain
+
+    @overrides(AbstractCore)
+    def connect_dcache(self, port: Port) -> None:
+        self.player.port = port
+
+    def set_reader(self, reader: DRTraceReader):
+        self.player.reader = reader
+
+    def set_memory_range(self, range: AddrRange):
+        self.player.compress_address_range = range

drtrace-stdlib.py

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+import m5
+import argparse
+from m5.objects import *
+
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.memory.hbm import HighBandwidthMemory
+from gem5.components.memory.single_channel import SingleChannelDDR4_2400
+from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
+
+from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
+    MESITwoLevelCacheHierarchy,
+)
+
+from gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import(
+    PrivateL1SharedL2CacheHierarchy,
+)
+
+from gem5.simulate.simulator import Simulator
+
+from dr_trace_player import DRTracePlayerGenerator
+
+parser = argparse.ArgumentParser(
+    description="A script to run google traces."
+)
+
+benchmark_choices = ["charlie", "delta", "merced", "whiskey"]
+
+parser.add_argument(
+    "--path",
+    type=str,
+    required=True,
+    help="Main directory containing the traces.",
+)
+
+parser.add_argument(
+    "--workload",
+    type=str,
+    required=True,
+    help="Input the benchmark program to execute.",
+    choices=benchmark_choices,
+)
+
+parser.add_argument(
+    "--players",
+    type=int,
+    required=True,
+    help="Input the number of players to use.",
+)
+
+parser.add_argument(
+    "--ruby",
+    type=int,
+    required=True,
+    help="Use with ruby or classic caches",
+)
+
+
+args = parser.parse_args()
+
+generator = DRTracePlayerGenerator(
+    "{}/{}/".format(args.path, args.workload),
+    num_cores=8,
+    max_ipc=8,
+    max_outstanding_reqs=16,
+)
+
+if args.ruby == 1:
+    cache_hierarchy = MESITwoLevelCacheHierarchy(
+        l1d_size="512kB",
+        l1d_assoc=8,
+        l1i_size="32kB",
+        l1i_assoc=2,
+        l2_size="1MB",
+        l2_assoc=16,
+        num_l2_banks=8,
+    )
+elif args.ruby == 0:
+    cache_hierarchy = PrivateL1SharedL2CacheHierarchy(
+        l1d_size="512kB",
+        l1d_assoc=8,
+        l1i_size="32kB",
+        l1i_assoc=2,
+        l2_size="1MB",
+        l2_assoc=16,
+    )
+else:
+    print("WRONG RUBY OPTION")
+    exit()
+
+memory = SingleChannelDDR4_2400(size="3GB")
+
+board = TestBoard(
+    clk_freq="5GHz",  # Ignored for these generators
+    generator=generator,  # We pass the traffic generator as the processor.
+    memory=memory,
+    # With no cache hierarchy the test board will directly connect the
+    # generator to the memory
+    cache_hierarchy=cache_hierarchy,
+)
+
+simulator = Simulator(board=board)
+simulator.run(100000000000)