Minor updates

architecture/RISCV/RV32IMFD.yml

@@ -3607,6 +3607,7 @@ instructions:
         CAPI.STACK.endFrame();
         CAPI.INTERRUPTS.setUserMode();
         CAPI.INTERRUPTS.clearHighlight();
+        CAPI.INTERRUPTS.globalEnable();
       help: Return from traps in M-mode, and mret copies mpie into mie, then
         sets mpie.
       properties:

architecture/RISCV/RV64IMFD.yml

@@ -3819,6 +3819,7 @@ instructions:
         CAPI.STACK.endFrame();
         CAPI.INTERRUPTS.setUserMode();
         CAPI.INTERRUPTS.clearHighlight();
+        CAPI.INTERRUPTS.globalEnable();
       help: Return from traps in M-mode, and mret copies mpie into mie, then
         sets mpie.
       properties:

examples/RISCV-32-interrupts/example1.s

@@ -3,11 +3,26 @@
 #
 
 .data
+	console_ctrl_addr: .word   0xF0000000
+   console_data_addr: .word   0xF0000008
 
 .text
    rti:
-      # ...
-
+      # t0 <- console data addr
+      la t0, console_data_addr
+      lw t0, 0(t0)
+
+      # t1 <- console ctrl addr
+      la t1, console_ctrl_addr
+      lw t1, 0(t1)
+
+      # console data <- a0
+      sw a0, 0(t0)
+
+      # console ctrl <- 11
+      li t0, 11
+      sw t0, 0(t1)
+
       # return from interrupt
       mret
 
@@ -16,17 +31,21 @@
       csrrw zero, mstatus, t0
       ori t0, t0, 8
       csrrw zero, mstatus, t0
-
+      
       # enable software interrupts (MSIE=1)
       csrrw zero, mie, t0
       ori t0, t0, 8
       csrrw zero, mie, t0
-
+      
       # load rti addr to mtvec
-      la t0, rti
+      la  t0, rti
+      li  t1, 2
+      sll t0, t0, t1
       csrrw zero, mtvec, t0
 
       # generate interrupt
+      li a7, 11
+      li a0, 'x'
       ecall
 
       li t0, 0

src/core/executor/InterruptManager.mts

@@ -289,7 +289,8 @@ export class InterruptManager {
 
     /** Checks if a type of interrupt is globally enabled */
     public isGlobalEnabled(): boolean {
-        return this.handler.isGlobalEnabled(this.status);
+        this.handler.isGlobalEnabled(this.status);
+        return this.status.globalEnabled ;
     }
 
     /** Clears a specific interrupt type */

tests/arch/__snapshots__/examples/RISCV-32-interrupts/example1.s.snap

@@ -2,47 +2,94 @@ export const snapshot = {};
 
 snapshot[`examples/RISCV-32-interrupts/example1.s 1`] = `
 {
-  display: "",
+  display: "x",
   error: false,
   keyboard: "",
   memory: {
-    "0": 48,
     "1": 32,
-    "10": 226,
-    "11": 147,
-    "13": 50,
-    "14": 144,
-    "15": 115,
-    "17": 82,
-    "18": 144,
-    "19": 115,
-    "21": 130,
-    "22": 226,
-    "23": 147,
-    "25": 82,
-    "26": 144,
-    "27": 115,
-    "3": 115,
+    "10": 162,
+    "102": 128,
+    "103": 103,
+    "11": 131,
+    "13": 32,
+    "14": 3,
+    "15": 23,
+    "16": 255,
+    "17": 67,
+    "18": 3,
+    "19": 19,
+    "2": 2,
+    "2097152": 240,
+    "2097156": 240,
+    "2097159": 8,
+    "21": 3,
+    "22": 35,
+    "23": 3,
+    "25": 162,
+    "26": 160,
+    "27": 35,
+    "29": 176,
+    "3": 151,
     "30": 2,
-    "31": 151,
-    "32": 254,
-    "33": 66,
-    "34": 130,
-    "35": 147,
-    "37": 34,
-    "38": 144,
+    "31": 147,
+    "33": 83,
+    "34": 32,
+    "35": 35,
+    "36": 48,
+    "37": 32,
     "39": 115,
+    "41": 50,
+    "42": 144,
     "43": 115,
-    "46": 2,
+    "45": 130,
+    "46": 226,
     "47": 147,
-    "5": 50,
-    "50": 128,
-    "51": 103,
-    "6": 144,
-    "7": 115,
-    "9": 130,
+    "49": 50,
+    "5": 66,
+    "50": 144,
+    "51": 115,
+    "53": 82,
+    "54": 144,
+    "55": 115,
+    "57": 130,
+    "58": 226,
+    "59": 147,
+    "6": 130,
+    "61": 82,
+    "62": 144,
+    "63": 115,
+    "66": 2,
+    "67": 151,
+    "68": 252,
+    "69": 2,
+    "7": 147,
+    "70": 130,
+    "71": 147,
+    "73": 32,
+    "74": 3,
+    "75": 19,
+    "77": 98,
+    "78": 146,
+    "79": 179,
+    "81": 34,
+    "82": 144,
+    "83": 115,
+    "85": 176,
+    "86": 8,
+    "87": 147,
+    "88": 7,
+    "89": 128,
+    "9": 2,
+    "90": 5,
+    "91": 19,
+    "95": 115,
+    "98": 2,
+    "99": 147,
   },
   registers: {
+    "x10,a0": "0x78",
+    "x17,a7": "0xb",
+    "x6,t1": "0x2",
     mie: "0x8",
     mtime: "0x3",
     pc: "0xfffffffe",