With a FPGA resource information extracted from Xilinx Vivado, the code visualizes resource map.
Three versions are available: 1)main tile types, 2)concise, 3)verbose. You can change the setting in the SETTING comment block in the code.
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With a FPGA resource information extracted from Xilinx Vivado, the code visualizes resource map.
Three versions are available: 1)main tile types, 2)concise, 3)verbose. You can change the setting in the SETTING comment block in the code.