SuperPMI: fix spurious arm asmdiffs from out-of-range BL relocs#130913
Open
AndyAyersMS wants to merge 1 commit into
Open
SuperPMI: fix spurious arm asmdiffs from out-of-range BL relocs#130913AndyAyersMS wants to merge 1 commit into
AndyAyersMS wants to merge 1 commit into
Conversation
The near-differ applies recorded relocations before comparing. For an arm32 direct BL (ARM32_THUMB_BRANCH24), applyRelocs substitutes a placeholder target when the code block lands more than +-16MB from the call target, so the two sides' immediates differ even though both call the same recorded target. Compare the recorded reloc kind and target instead. Also error out when base and diff JITs are the same module.
github-actions
Bot
added
the
area-CodeGen-coreclr
Member
Author
|
@jakobbotsch PTAL |
|
Azure Pipelines: Successfully started running 3 pipeline(s). 11 pipeline(s) were filtered out due to trigger conditions. There may be pipelines that require an authorized user to comment /azp run to run. Some pipeline(s) encountered errors during trigger evaluation. |
Contributor
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
Contributor
There was a problem hiding this comment.
Pull request overview
This PR updates SuperPMI’s asm-diffing and setup validation to reduce false-positive diffs on ARM32 and to prevent running with baseline/diff JITs that resolve to the same loaded module (which can corrupt shared global JIT state).
Changes:
- Add a startup check that errors out when baseline and diff JITs resolve to the same loaded module.
- Add
JitInstance::getModule()accessor to surface the loaded module handle for that check. - Adjust ARM32 offset comparison to treat certain relocation sites as semantically equivalent by consulting recorded relocation metadata rather than patched immediates.
Reviewed changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| src/coreclr/tools/superpmi/superpmi/superpmi.cpp | Adds validation to reject baseline/diff JITs that map to the same loaded module. |
| src/coreclr/tools/superpmi/superpmi/neardiffer.cpp | Adds an ARM32 relocation-aware equivalence check to avoid spurious asm diffs from patched BL immediates. |
| src/coreclr/tools/superpmi/superpmi/jitinstance.h | Exposes the loaded JIT module handle via a new accessor. |
Comment on lines
+579
to
+584
| if ((reloc1 != nullptr) && (reloc2 != nullptr) && (reloc1->fRelocType == reloc2->fRelocType) && | ||
| ((uint64_t)reloc1->target + (int32_t)reloc1->addlDelta == | ||
| (uint64_t)reloc2->target + (int32_t)reloc2->addlDelta)) | ||
| { | ||
| return true; | ||
| } |
This was referenced Jul 17, 2026
Open
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
For an arm32 direct BL (ARM32_THUMB_BRANCH24), applyRelocs substitutes a placeholder target when the code block lands more than +-16MB from the call target, so the two sides' immediates differ even though both call the same recorded target.
Compare the recorded reloc kind and target instead.
Also error out when base and diff JITs are the same module (this has burned me a few times).
Fixes #130736