XLS backend

.gitignore

@@ -7,6 +7,7 @@ sdist/
 *.egg-info/
 vivado_prj
 .vscode
+.idea
 my-hls-test
 *.tar.gz
 docs/_build

docs/backend/xls.rst

@@ -0,0 +1,47 @@
+============
+XLS
+============
+
+The XLS backend can convert hls4ml models into SystemVerilog via `Google XLS <https://google.github.io/xls/>`_, which can be converted to IP via **Vivado**.
+
+To enable XLS:
+.. code-block:: bash
+
+    pip install hls4ml[xls]
+
+hls4ml uses `pyxls <https://calad0i.github.io/pyxls/>`_ package to access XLS API.
+pyxls comes with batteries included, and a separate XLS installation is not required.
+
+Workflow
+=========================
+
+XLS backend preforms the following transformations:
+.. code-block::
+
+    hls4ml representation -> DSLX (<ProjectName>.x) -> XLS IR (<ProjectName>.ir) -> Optimized XLS IR (<ProjectName>.opt.ir) -> SystemVerilog (<ProjectName>.sv) -> IP
+
+`DSLX <https://google.github.io/xls/dslx_reference/>`_ is a DSL with Rust-like syntax.
+DSLX project generated by hls4ml in ``<OutputDir>/firmware`` contains the main module ``<ProjectName>.x``, layer modules ``layer_<LayerName>.x``, and helper modules in ``ap_types/`` and ``nnet_utils/``.
+You may work with this project either through hls4ml or using your own XLS toolchain.
+
+hls4ml calls XLS compiler to convert DSLX into `XLS IR <https://google.github.io/xls/ir_overview/>`_ format (``<ProjectName>.ir``) and then runs IR optimization passes (``<ProjectName>.opt.ir``).
+
+Then, hls4ml uses `XLS Codegen <https://google.github.io/xls/codegen_options/>`_ to generate SystemVerilog (``<ProjectName>.sv``) from IR, and calls **Vivado** for ``<OutputDir>/build_prj.tcl`` to generate IP.
+
+You can override default codegen options:
+.. code-block:: python
+
+    config = hls4ml.utils.config_from_keras_model(model)
+    # This sets hls_model.config['XLSCodegenFlags']
+    hls_model = hls4ml.converters.convert_from_keras_model(
+        model, hls_config=config, backend='XLS',
+        xls_codegen_flags={'delay_model': 'asap7', 'generator': 'pipeline', 'use_system_verilog': False}
+    )
+
+I/O Types and Strategy
+=========================
+
+Currently, only ``io_parallel`` is supported. ``Strategy`` is ignored.
+All operations are fully unrolled.
+
+XLS supports only signed ``FixedPoint`` type (similar to ``ap_fixed``).

docs/index.rst

@@ -39,6 +39,7 @@
     backend/catapult
     backend/quartus
     backend/sr
+    backend/xls
 
 .. toctree::
     :hidden:

docs/intro/setup.rst

@@ -203,6 +203,9 @@ Optional Dependencies
    # For symbolic regression
    pip install hls4ml[sr]
 
+   # For XLS backend
+   pip install hls4ml[xls]
+
    # For documentation building (developers)
    pip install hls4ml[doc]
 

docs/intro/status.rst

@@ -47,6 +47,7 @@ HLS backends:
 * Vitis HLS
 * Catapult HLS
 * oneAPI (experimental)
+* XLS (experimental)
 
 A summary of the on-going status of the ``hls4ml`` tool is in the table below.
 
@@ -79,6 +80,8 @@ A summary of the on-going status of the ``hls4ml`` tool is in the table below.
 +-----------------------+-----+-----+--------------+--------+--------+-----+
 | oneAPI (experimental) | ✅  | ✅  | ✅           | ❌     | ✅     | ❌  |
 +-----------------------+-----+-----+--------------+--------+--------+-----+
+| XLS (experimental)    | ✅  | ✅  | ❌           | ❌     | ❌     | ❌  |
++-----------------------+-----+-----+--------------+--------+--------+-----+
 
 Other feature notes:
 

hls4ml/backends/__init__.py

@@ -12,6 +12,7 @@
 from hls4ml.backends.catapult.catapult_backend import CatapultBackend  # isort: skip
 
 from hls4ml.backends.vitis.vitis_backend import VitisBackend  # isort: skip
+from hls4ml.backends.xls.xls_backend import XLSBackend
 
 
 def _register_builtin_backends():
@@ -23,6 +24,7 @@ def _register_builtin_backends():
     register_backend('SymbolicExpression', SymbolicExpressionBackend)
     register_backend('oneAPI', OneAPIBackend)
     register_backend('Libero', LiberoBackend)
+    register_backend('XLS', XLSBackend)
 
 
 _register_builtin_backends()