feat(phd-ch71): TRI-27 Coptic ISA & 3-bank Register File (Strand III)

docs/phd/bibliography.bib

@@ -3833,3 +3833,62 @@ @misc{rns_rust2025
   howpublished = {\url{https://crates.io/crates/reticulum}},
   note      = {Rust crate cited for L-DPC3 silicon strand routing layer (R1 CROWN compliance)}
 }
+
+% =============================================================================
+% Ch.71 — TRI-27 Coptic ISA entries (L-PHD-71, feat/phd-ch71)
+% Added: 2026-05-17. Anchor phi^2+phi^-2=3.
+% =============================================================================
+
+@book{patterson2014computer,
+  author    = {Patterson, David A. and Hennessy, John L.},
+  title     = {Computer Organization and Design: The Hardware/Software Interface},
+  edition   = {5th},
+  year      = {2014},
+  publisher = {Morgan Kaufmann / Elsevier},
+  address   = {Waltham, MA},
+  isbn      = {978-0-12-407726-3},
+  note      = {Q1 textbook (>20,000 citations). Cited in Ch.~71 for
+               RISC register file architecture, SPARC three-bank partition
+               conventions, and historical context for named register sets.}
+}
+
+@book{macwilliams1977theory,
+  author    = {MacWilliams, Florence Jessie and Sloane, Neil J. A.},
+  title     = {The Theory of Error-Correcting Codes},
+  year      = {1977},
+  publisher = {North-Holland Publishing Company},
+  address   = {Amsterdam},
+  isbn      = {978-0-444-85010-4},
+  note      = {Q1 foundational reference (>30,000 citations). Cited in Ch.~71
+               for GF(16) arithmetic, primitive polynomial $x^4+x+1$,
+               Frobenius endomorphism, and Fermat's little theorem for
+               finite fields. DOI unavailable (pre-DOI publication).}
+}
+
+@article{kanerva2009hyperdimensional,
+  author    = {Kanerva, Pentti},
+  title     = {Hyperdimensional Computing: An Introduction to Computing in
+               Distributed Representation with High-Dimensional Random Vectors},
+  journal   = {Cognitive Computation},
+  volume    = {1},
+  number    = {2},
+  pages     = {139--159},
+  year      = {2009},
+  publisher = {Springer},
+  doi       = {10.1007/s12559-009-9009-8},
+  note      = {Q1 journal (Springer Cognitive Computation). Cited in Ch.~71
+               for VSA bind/bundle/dot semantics (opcodes 0xDB--0xDE).}
+}
+
+@manual{xilinx2022ultrascale,
+  author       = {{Xilinx/AMD}},
+  title        = {{UltraScale} Architecture Reference Manual},
+  year         = {2022},
+  organization = {Xilinx / AMD},
+  number       = {AM004},
+  url          = {https://docs.xilinx.com/r/en-US/am004-versal-device-resources},
+  note         = {Manufacturer reference manual. Cited in Ch.~71 for LUT
+                  resource budgeting (352-LUT Sacred ALU target), switching
+                  activity power model, and timing analysis at 50\,MHz.
+                  Non-Q1 grey literature; within 20\% quota (R11).}
+}