PhD Glava 35 — Silicon Submission (Wave-16a integration)

docs/phd/bibliography.bib

@@ -3833,3 +3833,61 @@ @misc{rns_rust2025
   howpublished = {\url{https://crates.io/crates/reticulum}},
   note      = {Rust crate cited for L-DPC3 silicon strand routing layer (R1 CROWN compliance)}
 }
+
+% ============================================================
+% Glava 35 - Silicon Submission entries
+% Added by Vasilev Dmitrii admin(at)t27.ai feat/phd-glava-35-silicon-submission
+% ============================================================
+
+@article{modha_northpole_2023,
+  author    = {Modha, Dharmendra S. and Akopyan, Filipp and Arthur, John V.
+               and Cassidy, Andrew S. and Datta, Pallab and DeBole, Michael
+               and Esser, Steven K. and Garreau, Arnaud and Sawada, Jun
+               and Taba, Brian and Vineyard, Craig M. and Merolla, Paul A.},
+  title     = {{NorthPole}: Neural Inference at the Frontier of Energy, Space, and Time},
+  journal   = {Science},
+  volume    = {382},
+  number    = {6668},
+  pages     = {329--335},
+  year      = {2023},
+  doi       = {10.1126/science.adh1174},
+  url       = {https://doi.org/10.1126/science.adh1174},
+  note      = {IBM NorthPole architecture: 25 TOPS/W at Samsung 12 nm, zero-skip
+               clock gating, memory-near-compute. Primary design inspiration for
+               Trinity TRI-1 MAX zero-skip v2 (Glava 35, R-SI-1)}
+}
+
+@misc{platinum_aspdac2026,
+  author    = {Vasilev, Dmitrii},
+  title     = {Platinum {ASIC} Lever: {GF}(16) Polynomial Arithmetic for Ternary-Weight Neural Network Accelerators},
+  year      = {2025},
+  eprint    = {2511.21910},
+  archivePrefix = {arXiv},
+  primaryClass  = {cs.AR},
+  url       = {https://arxiv.org/abs/2511.21910},
+  note      = {ASP-DAC 2026 submission. Establishes the Platinum ASIC lever:
+               GF(2\^{}4) XOR-only multiplier, zero \$mul property (Platinum Theorem 1),
+               projected efficiency at 130 nm and 28 nm. Trinity TRI-1 MAX Wave-16a
+               is an empirical confirmation of this paper's Theorem 1. (R-SI-1)}
+}
+
+@misc{hailo10h_datasheet,
+  author    = {{Hailo Technologies Ltd.}},
+  title     = {Hailo-10H: High-Performance Edge {AI} Processor, Datasheet Rev.\ 1.2},
+  year      = {2024},
+  howpublished = {\url{https://hailo.ai/products/hailo-10/}},
+  note      = {Hailo-10H: 16 TOPS/W measured, TSMC 6 nm. Top-2 rival in Trinity
+               TRI-1 MAX comparative analysis. Used as verified benchmark for
+               projected 120 TOPS/W effective efficiency. (Glava 35, R5 HONEST)}
+}
+
+@misc{zenodo_19227877_phd,
+  author    = {Vasilev, Dmitrii},
+  title     = {Trinity {S}$^3${AI} -- Flos Aureus v6: Wave-16a {RTL}, Synthesis Reports, and Verification Testbenches},
+  year      = {2025},
+  howpublished = {\url{https://doi.org/10.5281/zenodo.19227877}},
+  doi       = {10.5281/zenodo.19227877},
+  note      = {Zenodo archive containing Wave-16a poly\_mesh.v RTL, gf16\_poly\_mul.v,
+               wave16a\_synth.log (0 \$mul, 1994 cells), 256/256 exhaustive test,
+               zero-skip v2 testbench. Anchor: phi\^{}2 + phi\^{}-2 = 3. (R-SI-1, R7)}
+}