Skip to content

glzhou97/DRCBench

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

4 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

DRCBench

DRCBench is a benchmark suite for evaluating layout pattern generation and verification under advanced semiconductor design rules. Built on the ASAP7 (7 nm FinFET) PDK, it offers diverse, realistic metal-layer patterns to bridge the gap between academic layout generation and industrial DRC verification. The primary intended usage is to evaluate the ability of existing ML algorithms to produce design-rule-compliant layouts and to measure corresponding diversity scores.

Repository layout

  • asap7/ – Git submodule mirroring the ASAP7 PDK. Consult asap7/README.md for installation notes, DRM, and Calibre deck guidance.
  • M1_data/ – Metal-1 benchmark set derived from the ASAP7 7.5-track standard-cell library:
    • gds/ – 212 single-layer GDS extracts (*_ASAP7_75t_R_M1.gds) ready for import into KLayout, Calibre, or other DRC engines.
    • png/ – Raster previews for quick visual inspection (*_ASAP7_75t_R_M1.png) plus a single INVx1_test.png example used during dataset validation.

Getting started

  1. Clone the repository with submodules to pull the ASAP7 collateral:
    git clone --recurse-submodules https://github.com/glzhou97/DRCBench.git
    # or, if already cloned:
    git submodule update --init --recursive
  2. Follow the instructions in asap7/asap7_pdk_r1p7/README_ASAP7PDK_INSTALL_201210a.txt to install the PDK and, if needed, download the proprietary Calibre decks from the ASAP7 distribution site.
  3. Point your DRC or layout-viewing tool to the appropriate tech files (e.g., the KLayout .lyp and .lyt configs or Calibre rule decks) when loading patterns from M1_data/gds.

Working with the Metal-1 dataset

  • Coverage Currently, this dataset only contain patterns that can cover M1.S.4/6 rule and related area and width rules. PNG files are provided for model training. Expansion to additional rule categories is ongoing.
  • Inspection: Open any pattern GDS in KLayout, Virtuoso, or an equivalent tool to visualize the metal geometries. The PNG thumbnails provide at-a-glance previews to help triage interesting cases before loading the full layout.
  • Rule checking: Use the official ASAP7 Calibre decks (recommended), or translate the rules into your in-house checker, to benchmark false positives/negatives and runtime on the provided patterns.

img1 img2 img3

Licensing and citation

  • The ASAP7 PDK and libraries are distributed under the BSD 3-Clause license; see asap7/LICENSE for details.

Contact

Please email guanglei.zhou@duke.edu if you are interested in collaborating. Issues, questions, or contributions are welcome via GitHub pull requests or the issue tracker.

About

DRCBench is a benchmark suite for evaluating layout pattern generation and verification under advanced semiconductor design rules. Built on the ASAP7 (7 nm FinFET) PDK, it offers diverse, realistic metal-layer patterns to bridge the gap between academic layout generation and industrial DRC verification.

Resources

Stars

1 star

Watchers

0 watching

Forks

Releases

No releases published

Packages

 
 
 

Contributors