Jacquard is a GPU-accelerated RTL logic simulator. Like a Jacquard loom weaving patterns from punched cards, Jacquard maps gate-level netlists onto a virtual manycore Boolean processor and executes them on GPUs, delivering 5-40X speedup over CPU-based RTL simulators.
Jacquard builds on the excellent GEM research by Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, and Haoxing Ren at NVIDIA Research. Jacquard extends their work with:
- Metal backend for Apple Silicon Macs (in addition to the original CUDA backend)
- Liberty timing support — load real cell delays from Liberty files (e.g. SKY130) for timing-annotated simulation
- SDF back-annotation — post-layout timing from Standard Delay Format files
- Setup/hold violation detection — both CPU and GPU-side checking
- Significant performance optimizations to the partition mapping pipeline
- CI/CD with automated testing across all three backends
GPU-accelerated gate-level simulation with real cell timing is live across all
three backends. For the per-backend feature status — Liberty parsing, SDF
back-annotation, setup/hold violation detection, and the structured
--timing-report — see Timing Simulation.
CHANGELOG.md tracks released and unreleased changes.
Required for building: the Rust toolchain (2021 edition). A GPU SDK is required only for the backend you build against.
Optional tooling used by specific workflows:
| Tool | Used for | macOS (Homebrew) | Linux (Debian/Ubuntu) |
|---|---|---|---|
flatc |
regenerating timing-IR bindings when editing crates/timing-ir/schemas/timing_ir.fbs |
brew install flatbuffers |
apt install flatbuffers-compiler |
mdbook |
building docs locally | brew install mdbook |
cargo install mdbook |
| OpenSTA | building the vendored vendor/opensta/ for use by opensta-to-ir and the timing-correctness CI corpus |
brew bundle --file vendor/opensta/Brewfile then run scripts/build-opensta.sh |
see vendor/opensta/Dockerfile.ubuntu22.04, then run scripts/build-opensta.sh |
Contributors editing only Rust / C++ / kernel sources do not need flatc or OpenSTA; the IR bindings are checked in and the OpenSTA build is only required when running the timing-correctness regression corpus.
Just want to install Jacquard? On macOS (Apple Silicon / Metal):
brew install gpu-eda/homebrew-tap/jacquardSee Installation for
cargo binstall, the prebuilt tarball, and thenetlist-graphPyPI companion. The from-source build below is the contributor path — and the route for Linux CUDA / HIP.
git clone https://github.com/gpu-eda/Jacquard.git
cd Jacquard
git submodule update --init --recursivecargo build -r --features metal --bin jacquardRequires CUDA toolkit installed.
cargo build -r --features cuda --bin jacquardBy default the kernel is built with PTX for compute_50 plus SASS for sm_70
and sm_80; newer GPUs run via PTX JIT at first load. To target a specific
architecture, set JACQUARD_CUDA_ARCH, which is passed straight to nvcc as
-arch=<value>:
# Local dev — build native SASS for the GPU in THIS machine (fastest, no
# first-load JIT). Example: an sm_120 Blackwell card.
JACQUARD_CUDA_ARCH=native cargo build -r --features cuda --bin jacquard
# Distribution — portable SASS for every major arch the toolkit knows, plus
# PTX for the newest (needs CUDA ≥ 12.8 to include Blackwell sm_100/sm_120).
JACQUARD_CUDA_ARCH=all-major cargo build -r --features cuda --bin jacquardAny nvcc -arch value works (native, all-major, all, sm_120, …).
Leave it unset to keep the default behavior.
Simulate a gate-level netlist with a VCD input waveform:
# Metal (macOS) - use NUM_BLOCKS=1
cargo run -r --features metal --bin jacquard -- sim design.gv input.vcd output.vcd 1
# CUDA (Linux) - set NUM_BLOCKS to 2x your GPU's SM count
cargo run -r --features cuda --bin jacquard -- sim design.gv input.vcd output.vcd NUM_BLOCKS
# With SDF timing back-annotation:
cargo run -r --features metal --bin jacquard -- sim design.gv input.vcd output.vcd 1 \
--sdf design.sdf --sdf-corner typPartitioning (mapping the design to GPU blocks) happens automatically at startup.
See Getting Started to run bundled designs in seconds, or the Synthesis Flow for synthesis preparation, VCD scope handling, and running your own RTL.
Browse the full documentation online or build it locally with mdbook:
mdbook serve # opens at http://localhost:3000Jacquard is a gate-level emulator: the input to sim / cosim is a
synthesized gate-level Verilog netlist (structural Verilog mapped to
aigpdk / SKY130 / GF180MCU cells).
Behavioral RTL is the intended design input — through a synthesis step. Bring
your RTL, synthesize it to a gate-level netlist (Yosys or a commercial tool;
synthesis quality sets Jacquard's speed, so it's a deliberate step), then
simulate. The full flow — memory mapping + logic synthesis to aigpdk.lib — is
in the Synthesis Flow
guide.
- Feed it: a synthesized netlist (
design.gv), or your RTL after synthesis. - Don't feed it raw behavioral RTL (
always/if/case/reg/params) — the synthesizer elaborates those away first. - Full supported netlist syntax + SystemVerilog/SVA status: Input netlist language.
An integrated
jacquard build design.von-ramp (Yosys embedded via YoWASP, no manual synthesis) is planned — ADR 0021 / #162.
jacquard simtakes a static VCD input waveform. For reactive testbenches,jacquard cosimruns peripheral models (SPI flash, UART, JTAG — including an interactive--jtag-server— and Wishbone / APB3 bus tracing) as GPU kernels alongside the design, so inputs can depend on design outputs cycle-by-cycle.- Edge-triggered flip-flops only in the logic — a raw
LATCHcell in the gate-level netlist is rejected (async set/reset on flip-flops is fine; async reset is not the restriction). The two common structured latch uses are supported through their own paths: clock gating via theCKLNQDintegrated clock-gating cell (below), and latch / register-file memory mapped through the memory-synthesis step (memory_libmap→ RAM; see Synthesis Flow). - Clock gates must use
CKLNQD(fromaigpdk.v) or the equivalent clock-gate cells from the SKY130 or GF180MCU PDKs.
Pre-synthesized benchmark designs are in benchmarks/dataset/ (git submodule). See benchmarks/README.md for instructions.
Available designs: NVDLA, Rocket, Gemmini.
Jacquard builds on the GEM research. Please cite the original paper if you find this work useful.
@inproceedings{gem,
author = {Guo, Zizheng and Zhang, Yanqing and Wang, Runsheng and Lin, Yibo and Ren, Haoxing},
booktitle = {Proceedings of the 62nd Annual Design Automation Conference 2025},
organization = {IEEE},
title = {{GEM}: {GPU}-Accelerated Emulator-Inspired {RTL} Simulation},
year = {2025}
}Apache-2.0. See LICENSE for details.