Migrate NXP Kinetis khci to chipidea ci_fs (device + host) + fixes

README.rst

@@ -239,9 +239,7 @@ Supported CPUs
 +--------------+---------+-------------------+--------+------+-----------+------------------------+--------------------+
 | NXP          | iMXRT   | RT 10xx, 11xx     | ✅     | ✅   | ✅        | ci_hs, ehci            |                    |
 |              +---------+-------------------+--------+------+-----------+------------------------+--------------------+
-|              | Kinetis | KL                | ✅     | 🟡   | ❌        | ci_fs, khci            |                    |
-|              |         +-------------------+--------+------+-----------+------------------------+--------------------+
-|              |         | K32L2             | ✅     |      | ❌        | khci                   | ci_fs variant      |
+|              | Kinetis | KL, K32L          | ✅     | 🟡   | ❌        | ci_fs                  |                    |
 |              +---------+-------------------+--------+------+-----------+------------------------+--------------------+
 |              | LPC     | 11u, 13, 15       | ✅     | ❌   | ❌        | lpc_ip3511             |                    |
 |              |         +-------------------+--------+------+-----------+------------------------+--------------------+

examples/host/cdc_msc_hid/only.txt

@@ -3,6 +3,7 @@ family:samd21
 family:samd5x_e5x
 mcu:CH32V20X
 mcu:KINETIS_KL
+mcu:KINETIS_K
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX

examples/host/device_info/only.txt

@@ -4,6 +4,7 @@ family:samd21
 family:samd5x_e5x
 mcu:CH32V20X
 mcu:KINETIS_KL
+mcu:KINETIS_K
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX

hw/bsp/kinetis_k/family.c

@@ -35,10 +35,25 @@
 #include "fsl_clock.h"
 #include "fsl_uart.h"
 #include "fsl_sysmpu.h"
+#include "common/tusb_fifo.h"
 
 #include "board/clock_config.h"
 #include "board/pin_mux.h"
 
+#ifdef UART_DEV
+// RX ring buffer filled by the RDRF interrupt so board_uart_read() is non-blocking
+// and does not drop bytes to UART overrun (see stm32 family for reference).
+static uint8_t   uart_rx_ff_buf[32];
+static tu_fifo_t uart_rx_ff;
+
+void UART0_RX_TX_IRQHandler(void) {
+  if (UART_DEV->S1 & UART_S1_RDRF_MASK) {
+    uint8_t byte = UART_DEV->D; // reading S1 then D clears RDRF (and any overrun)
+    tu_fifo_write(&uart_rx_ff, &byte);
+  }
+}
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -89,6 +104,9 @@ void board_init(void) {
       .enableRx = true
   };
   UART_Init(UART_DEV, &uart_config, UART_CLOCK);
+  tu_fifo_config(&uart_rx_ff, uart_rx_ff_buf, sizeof(uart_rx_ff_buf), false);
+  UART_DEV->C2 |= UART_C2_RIE_MASK; // enable RX data register full interrupt
+  NVIC_EnableIRQ(UART0_RX_TX_IRQn);
 #endif
 
   // USB
@@ -112,14 +130,11 @@ uint32_t board_button_read(void) {
 }
 
 int board_uart_read(uint8_t *buf, int len) {
-  (void) buf;
-  (void) len;
 #ifdef UART_DEV
-  // Read blocking will block until there is data
-//  UART_ReadBlocking(UART_DEV, buf, len);
-//  return len;
-  return 0;
+  return (int) tu_fifo_read_n(&uart_rx_ff, buf, (uint16_t) len);
 #else
+  (void) buf;
+  (void) len;
   return 0;
 #endif
 }
@@ -144,6 +159,20 @@ int board_uart_write(void const *buf, int len) {
 #endif
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  // Kinetis 128-bit Unique Identification Register (SIM->UIDH/UIDMH/UIDML/UIDL)
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 16;
+
+  id32[0] = SIM->UIDH;
+  id32[1] = SIM->UIDMH;
+  id32[2] = SIM->UIDML;
+  id32[3] = SIM->UIDL;
+
+  return len;
+}
+
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 

hw/bsp/kinetis_k/family.cmake

@@ -63,7 +63,7 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
-    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    ${TOP}/src/portable/chipidea/ci_fs/hcd_ci_fs.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${TARGET} PUBLIC

hw/bsp/kinetis_k/family.mk

@@ -17,8 +17,8 @@ LDFLAGS += \
   --specs=nosys.specs --specs=nano.specs \
 
 SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	src/portable/nxp/khci/hcd_khci.c \
+	src/portable/chipidea/ci_fs/dcd_ci_fs.c \
+	src/portable/chipidea/ci_fs/hcd_ci_fs.c \
 	$(MCU_DIR)/system_${MCU_VARIANT}.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \

hw/bsp/kinetis_k32l/family.cmake

@@ -64,8 +64,8 @@ function(family_configure_example TARGET RTOS)
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    ${TOP}/src/portable/nxp/khci/dcd_khci.c
-    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+    ${TOP}/src/portable/chipidea/ci_fs/hcd_ci_fs.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${TARGET} PUBLIC

hw/bsp/kinetis_k32l/family.mk

@@ -13,8 +13,8 @@ LDFLAGS += \
   -specs=nosys.specs -specs=nano.specs
 
 SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	src/portable/nxp/khci/hcd_khci.c \
+	src/portable/chipidea/ci_fs/dcd_ci_fs.c \
+	src/portable/chipidea/ci_fs/hcd_ci_fs.c \
 	$(MCUX_DEVICES)/K32L/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \
 	$(MCUX_DEVICES)/K32L/$(MCU_VARIANT)/drivers/fsl_clock.c \
 	$(MCUX_CORE)/drivers/gpio/fsl_gpio.c \

hw/bsp/kinetis_kl/family.cmake

@@ -62,7 +62,7 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
-    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    ${TOP}/src/portable/chipidea/ci_fs/hcd_ci_fs.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${TARGET} PUBLIC

hw/bsp/kinetis_kl/family.mk

@@ -17,8 +17,8 @@ LDFLAGS += \
   -specs=nosys.specs -specs=nano.specs \
 
 SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	src/portable/nxp/khci/hcd_khci.c \
+	src/portable/chipidea/ci_fs/dcd_ci_fs.c \
+	src/portable/chipidea/ci_fs/hcd_ci_fs.c \
 	$(MCU_DIR)/system_$(MCU).c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \

src/portable/chipidea/ci_fs/dcd_ci_fs.c

@@ -175,6 +175,17 @@ static void process_tokdne(uint8_t rhport)
     return;
   }
   const unsigned length = ep->length;
+
+  /* Transfer is complete. For OUT, a multi-packet transfer speculatively arms the
+   * sibling (even/odd) BDT to avoid NAK. When the transfer ends early - e.g. the host
+   * sends a short packet before filling both buffers - that sibling is left armed
+   * (own=1). A leftover armed BDT desyncs the even/odd ping-pong so the next OUT
+   * packet lands in the wrong buffer half (buffer + max_packet_size instead of
+   * buffer), making the stack read stale data. Disarm it here. */
+  if (dir == TUSB_DIR_OUT) {
+    _dcd.bdt[epnum][dir][odd ^ 1].own = 0;
+  }
+
   dcd_event_xfer_complete(rhport,
                           tu_edpt_addr(epnum, dir),
                           length - remaining, XFER_RESULT_SUCCESS, true);