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Merged
pull merged 6 commits into from
Feb 13, 2026
Merged

[pull] master from ckormanyos:master #74

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da354c1
Get esp32_p4 benches running via hybrid startup
ckormanyos Feb 13, 2026
b15118a
Update benchmark docs
ckormanyos Feb 13, 2026
1f300ff
Merge pull request #724 from ckormanyos/esp32_p4_benches
ckormanyos Feb 13, 2026
2e786dc
Cleanup esp32_p4 Stdlib manual funcs
ckormanyos Feb 13, 2026
5b318d7
Clarify comments and dates
ckormanyos Feb 13, 2026
b345212
Merge pull request #725 from ckormanyos/cleanup_esp32_p4
ckormanyos Feb 13, 2026
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4 changes: 4 additions & 0 deletions ref_app/src/app/benchmark/readme.md
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Expand Up @@ -85,6 +85,7 @@ The benchmark used is a ${\sim}100$ decimal digit AGM $\pi$ calculation.
|---------------------------|-----------------|------------|
| `am6254_soc` | 0.37 | 1.0 |
| `am335x` | 1.5 | 4.1 |
| `xtensa_esp32_p4` | 2.5 | 6.8 |
| `stm32f446` | 5.1 | 14 |
| `rpi_pico2_rp2350` | 6.3 | 17 |
| `wch_ch32v307` | 8.0 | 22 |
Expand Down Expand Up @@ -121,6 +122,9 @@ running the benchmark in about $10~{\text{ms}}$.
Running on only one core (core0) of the $32$-bit
controller of the `xtensa_esp32_s3` board results in
a runtime of $9.1~{\text{ms}}$ for the calculation.
The next generation `xtensa_esp32_p4` with a dual RISC-V core
architecture is significantly faster coming in at $2.5~{\text{ms}}$
(running the benchmark on one core).

Using only one core (core1) on the $32$-bit ARM(R) Cortex(R) M0+
controller of the `rpi_pico_rp2040` board results in a calculation
Expand Down
8 changes: 4 additions & 4 deletions ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h
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Expand Up @@ -5,8 +5,8 @@
// or copy at http://www.boost.org/LICENSE_1_0.txt)
//

#ifndef MCAL_BENCHMARK_2014_04_16_H_
#define MCAL_BENCHMARK_2014_04_16_H_
#ifndef MCAL_BENCHMARK_2014_04_16_H
#define MCAL_BENCHMARK_2014_04_16_H

#include <mcal_port.h>
#include <mcal_reg.h>
Expand All @@ -17,8 +17,8 @@
{
namespace benchmark
{
typedef mcal::port::port_pin<UINT32_C(8)> benchmark_port_type;
typedef mcal::port::port_pin<unsigned { UINT8_C(18) }> benchmark_port_type;
}
}

#endif // MCAL_BENCHMARK_2014_04_16_H_
#endif // MCAL_BENCHMARK_2014_04_16_H
185 changes: 94 additions & 91 deletions ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h
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Expand Up @@ -24,8 +24,8 @@

******************************************************************************************/

#ifndef MCAL_PORT_2025_02_22_H
#define MCAL_PORT_2025_02_22_H
#ifndef MCAL_PORT_2026_02_13_H
#define MCAL_PORT_2026_02_13_H

#include <mcal_reg.h>

Expand All @@ -46,122 +46,71 @@
private:
static constexpr std::uint8_t my_pin { static_cast<std::uint8_t>(PortIndex) };

static constexpr uintptr_t GPIO_BASE { (uintptr_t) UINT32_C(0x500E0000) };
static constexpr uintptr_t LP_IO_MUX_BASE { (uintptr_t) UINT32_C(0x5012B000) };
static constexpr uintptr_t IO_MUX_BASE { (uintptr_t) UINT32_C(0x500E1000) };

typedef union
{
volatile uint32_t reg;
volatile std::uint32_t reg;

struct
{
volatile uint32_t MCU_OE : 1;
volatile uint32_t SLP_SEL : 1;
volatile uint32_t MCU_WPD : 1;
volatile uint32_t MCU_WPU : 1;
volatile uint32_t MCU_IE : 1;
volatile uint32_t MCU_DRV : 2;
volatile uint32_t FUN_WPD : 1;
volatile uint32_t FUN_WPU : 1;
volatile uint32_t FUN_IE : 1;
volatile uint32_t FUN_DRV : 2;
volatile uint32_t MCU_SEL : 3;
volatile uint32_t FILTER_EN : 1;
uint32_t : 16;
volatile std::uint32_t MCU_OE : 1;
volatile std::uint32_t SLP_SEL : 1;
volatile std::uint32_t MCU_WPD : 1;
volatile std::uint32_t MCU_WPU : 1;
volatile std::uint32_t MCU_IE : 1;
volatile std::uint32_t MCU_DRV : 2;
volatile std::uint32_t FUN_WPD : 1;
volatile std::uint32_t FUN_WPU : 1;
volatile std::uint32_t FUN_IE : 1;
volatile std::uint32_t FUN_DRV : 2;
volatile std::uint32_t MCU_SEL : 3;
volatile std::uint32_t FILTER_EN : 1;
std::uint32_t : 16;
}
bit;
}
IO_MUX_GPIO;

typedef union
{
volatile uint32_t reg;
volatile std::uint32_t reg;

struct
{
volatile uint32_t OUT_SEL : 9;
volatile uint32_t INV_SEL : 1;
volatile uint32_t OEN_SEL : 1;
volatile uint32_t OEN_INV_SEL : 1;
uint32_t : 20;
volatile std::uint32_t OUT_SEL : 9;
volatile std::uint32_t INV_SEL : 1;
volatile std::uint32_t OEN_SEL : 1;
volatile std::uint32_t OEN_INV_SEL : 1;
std::uint32_t : 20;
}
bit;
}
GPIO_FUNC_OUT_SEL_CFG;

typedef union
{
volatile uint32_t reg;
volatile std::uint32_t reg;

struct
{
volatile uint32_t REG_PAD_DRV : 2;
volatile uint32_t REG_PAD_RDE : 1;
volatile uint32_t REG_PAD_RUE : 1;
volatile uint32_t REG_PAD_MUX_SEL : 1;
volatile uint32_t REG_PAD_FUN_SEL : 2;
volatile uint32_t REG_PAD_SLP_SEL : 1;
volatile uint32_t REG_PAD_SLP_IE : 1;
volatile uint32_t REG_PAD_SLP_OE : 1;
volatile uint32_t REG_PAD_FUN_IE : 1;
volatile uint32_t REG_PAD_FILTER_EN : 1;
uint32_t : 20;
volatile std::uint32_t REG_PAD_DRV : 2;
volatile std::uint32_t REG_PAD_RDE : 1;
volatile std::uint32_t REG_PAD_RUE : 1;
volatile std::uint32_t REG_PAD_MUX_SEL : 1;
volatile std::uint32_t REG_PAD_FUN_SEL : 2;
volatile std::uint32_t REG_PAD_SLP_SEL : 1;
volatile std::uint32_t REG_PAD_SLP_IE : 1;
volatile std::uint32_t REG_PAD_SLP_OE : 1;
volatile std::uint32_t REG_PAD_FUN_IE : 1;
volatile std::uint32_t REG_PAD_FILTER_EN : 1;
std::uint32_t : 20;
}
bit;
}
LP_IO_MUX_GPIO;

static void gpio_cfg_output()
{
if((unsigned) my_pin <= 54u)
{
volatile IO_MUX_GPIO* pIO_MUX_GPIO = (volatile IO_MUX_GPIO*)(IO_MUX_BASE + 4u + 4u * (unsigned) my_pin);
volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG = (volatile GPIO_FUNC_OUT_SEL_CFG*)(GPIO_BASE + 0x558ul + 4u * (unsigned) my_pin);
volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO = (volatile LP_IO_MUX_GPIO*)(LP_IO_MUX_BASE + 8u + 4u * (unsigned) my_pin);
volatile uint32_t* pGPIO_OUTx_W1TC = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 0x0Cu : 0x18u));
volatile uint32_t* pGPIO_ENABLE1x_W1TS = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 0x24u : 0x30u));

/* configure the pinmux */
pIO_MUX_GPIO->bit.FUN_DRV = 2;
pIO_MUX_GPIO->bit.FUN_IE = 0;
pIO_MUX_GPIO->bit.MCU_SEL = 1;

/* set the output configuration */
pGPIO_FUNC_OUT_SEL_CFG->bit.OUT_SEL = 256;
pGPIO_FUNC_OUT_SEL_CFG->bit.OEN_SEL = 1;

if((unsigned) my_pin < 16u)
{
/* make LP_GPIO use HP_IO_MUX */
pLP_IO_MUX_GPIO->bit.REG_PAD_MUX_SEL = 0;
}

/* drive the IO output low */
*pGPIO_OUTx_W1TC = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
*pGPIO_ENABLE1x_W1TS = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
}
}

static void gpio_set_output_level(const uint8_t level)
{
if(((unsigned) my_pin <= 54u) && ((unsigned) level <= 1u))
{
volatile uint32_t* pGPIO_OUT_W1Tx = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 8u : 0x14u) + (((unsigned) level == 1u) ? (0u) : (4u)));

*pGPIO_OUT_W1Tx = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
}
}

static void gpio_toggle_output_level()
{
if((unsigned) my_pin <= 54u)
{
volatile uint32_t* pGPIO_OUT = (volatile uint32_t*)(GPIO_BASE + 4u + (((unsigned) my_pin < 32u) ? 0u : 0xCu));

*pGPIO_OUT ^= (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
}
}
static void gpio_cfg_output();
static void gpio_set_output_level(const std::uint8_t level);
static void gpio_toggle_output_level();

public:
static auto set_direction_output() -> void
Expand Down Expand Up @@ -193,7 +142,61 @@
gpio_toggle_output_level();
}
};
}
}

#endif // MCAL_PORT_2025_02_22_H
template<const unsigned PortIndex>
void port_pin<PortIndex>::gpio_cfg_output()
{
if(unsigned { my_pin } <= 54u)
{
volatile IO_MUX_GPIO* pIO_MUX_GPIO { reinterpret_cast<volatile IO_MUX_GPIO*> (mcal::reg::io_mux_base + 4u + 4u * unsigned { my_pin }) };
volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG { reinterpret_cast<volatile GPIO_FUNC_OUT_SEL_CFG*>(mcal::reg::gpio_base + 0x558u + 4u * unsigned { my_pin }) };
volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO { reinterpret_cast<volatile LP_IO_MUX_GPIO*> (mcal::reg::lp_io_mux_base + 8u + 4u * unsigned { my_pin }) };
volatile std::uint32_t* pGPIO_OUTx_W1TC { reinterpret_cast<volatile std::uint32_t*> (mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 0x0Cu : 0x18u)) };
volatile std::uint32_t* pGPIO_ENABLE1x_W1TS { reinterpret_cast<volatile std::uint32_t*> (mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 0x24u : 0x30u)) };

// Configure the pinmux.
pIO_MUX_GPIO->bit.FUN_DRV = 2;
pIO_MUX_GPIO->bit.FUN_IE = 0;
pIO_MUX_GPIO->bit.MCU_SEL = 1;

// Set the output configuration.
pGPIO_FUNC_OUT_SEL_CFG->bit.OUT_SEL = 256;
pGPIO_FUNC_OUT_SEL_CFG->bit.OEN_SEL = 1;

if(unsigned { my_pin } < 16u)
{
// Make LP_GPIO use HP_IO_MUX.
pLP_IO_MUX_GPIO->bit.REG_PAD_MUX_SEL = 0;
}

// Drive the IO output low.
*pGPIO_OUTx_W1TC = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
*pGPIO_ENABLE1x_W1TS = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
}
}

template<const unsigned PortIndex>
void port_pin<PortIndex>::gpio_set_output_level(const uint8_t level)
{
if((unsigned { my_pin } <= 54u) && (unsigned { level } <= 1u))
{
volatile std::uint32_t* pGPIO_OUT_W1Tx { reinterpret_cast<volatile std::uint32_t*>(mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 8u : 0x14u) + (((unsigned) level == 1u) ? (0u) : (4u))) };

*pGPIO_OUT_W1Tx = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
}
}

template<const unsigned PortIndex>
void port_pin<PortIndex>::gpio_toggle_output_level()
{
if(unsigned { my_pin } <= 54u)
{
volatile std::uint32_t* pGPIO_OUT { reinterpret_cast<volatile std::uint32_t*>(mcal::reg::gpio_base + 4u + ((unsigned { my_pin } < 32u) ? 0u : 0xCu)) };

*pGPIO_OUT ^= static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
}
}
} // namespace port
} // namespace mcal

#endif // MCAL_PORT_2026_02_13_H
4 changes: 4 additions & 0 deletions ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h
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Expand Up @@ -21,6 +21,10 @@
constexpr std::uint32_t clint_mtimecmph { clint_base + static_cast<std::uint32_t>(UINT32_C(0x00004004)) };

constexpr std::uint32_t clic_base { UINT32_C(0x20800000) };

constexpr std::uint32_t gpio_base { UINT32_C(0x500E0000) };
constexpr std::uint32_t lp_io_mux_base { UINT32_C(0x5012B000) };
constexpr std::uint32_t io_mux_base { UINT32_C(0x500E1000) };
}
}

Expand Down
3 changes: 3 additions & 0 deletions ref_app/target.vcxproj
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Expand Up @@ -1287,6 +1287,9 @@
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Appli\main_cores.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Startup\intvect.c" />
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Startup\Startup.c" />
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\StdLib\StdLib.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt0_init_ram.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt1.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0_init_ram.cpp" />
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt1.cpp" />
Expand Down
12 changes: 12 additions & 0 deletions ref_app/target.vcxproj.filters
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Expand Up @@ -358,6 +358,9 @@
<Filter Include="micros\xtensa_esp32_p4\startup\Code\Startup">
<UniqueIdentifier>{17889d6f-9174-40cb-bcad-01e3995207e5}</UniqueIdentifier>
</Filter>
<Filter Include="micros\xtensa_esp32_p4\startup\Code\StdLib">
<UniqueIdentifier>{65c5c603-a019-41d0-8a19-3cadaca7fd3c}</UniqueIdentifier>
</Filter>
</ItemGroup>
<ItemGroup>
<None Include="target\app\make\app_files.gmk">
Expand Down Expand Up @@ -1175,6 +1178,15 @@
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Appli\main_cores.cpp">
<Filter>micros\xtensa_esp32_p4\startup\Code\Appli</Filter>
</ClCompile>
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt1.cpp">
<Filter>micros\xtensa_esp32_p4\startup</Filter>
</ClCompile>
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt0_init_ram.cpp">
<Filter>micros\xtensa_esp32_p4\startup</Filter>
</ClCompile>
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\StdLib\StdLib.cpp">
<Filter>micros\xtensa_esp32_p4\startup\Code\StdLib</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<Text Include="target\micros\bcm2835_raspi_b\startup\SD_CARD\PiZero\config.txt">
Expand Down
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