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1. PY_UVM_Framework PY_UVM_Framework Public

   This repo contain the PY-UVM Framework for different RISC-V Cores

   Python 32 1

2. SAP_FPU SAP_FPU Public

   This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.

   Verilog 18 4

3. RISCV_Pipeline_Core RISCV_Pipeline_Core Public

   This repository contains the design files of RISC-V Pipeline Core

   Verilog 65 16

4. PY_UVM_Tutorial PY_UVM_Tutorial Public

   This repository will contain all the files regarding the Py-UVM tutorial

   Python 3 1

5. RISCV_Single_Cycle_Core RISCV_Single_Cycle_Core Public

   This repository contains the design files of RISC-V Single Cycle Core

   Verilog 77 18

6. Logisim Logisim Public

   Mastering Digital Logic Design with Logisim: From Basics to CPU

   8 1