Genify is a structured, end-to-end learning program that bridges Artificial Intelligence and Computer Architecture, with a strong focus on Machine Learning, Deep Learning, RISC-V, and Hardware Design using HDLs.
Topics Covered:
- Genify Overview
- Python Basics
- Digital Logic Design
Topics Covered:
- Object-Oriented Programming (OOP) in Python
- RISC-V Instruction Set Architecture (ISA)
Topics Covered:
- Data Cleaning
- Feature Engineering
- Data Preprocessing
- Types of Machine Learning
Topics Covered:
- Machine Learning
- Supervised Machine Learning
Topics Covered:
- Unsupervised Machine Learning
- Reinforcement Learning
Topics Covered:
- Artificial Neural Networks (ANNs)
- RISC-V Revision
Topics Covered:
- RISC-V Single-Cycle Core Deep Dive
Topics Covered:
- Artificial Neural Networks (ANNs)
Topics Covered:
- Convolutional Neural Networks (CNNs)
Topics Covered:
- Advanced CNN Concepts
Topics Covered:
- Introduction to HDLs
- CHISEL HDL
- Verilog HDL
Topics Covered:
- Recurrent Neural Networks (RNNs)
Topics Covered:
- Long Short-Term Memory (LSTM) Networks
- Introduction to HDLs
- CHISEL
- SystemVerilog
Topics Covered:
- Transformers Overview
- Self-Attention Mechanism
Topics Covered:
- Deep Dive into Self-Attention
Topics Covered:
- Multi-Head Attention
- Positional Encoding
- Encoder Architecture
Topics Covered:
- Transformers Recap
- Decoder Architecture
Topics Covered:
- LLM Inferencing
- Prompt Engineering
- Vector Databases
Topics Covered:
- Tokenization
- Vector Databases
- Semantic Search
- LLM Ecosystem Overview
- LangChain
Topics Covered:
- Retrieval Augmented Generation (RAG)
Topics Covered:
- AI Agents
- AI Agent Frameworks
- Python
- Machine Learning & Deep Learning
- RISC-V Architecture
- Verilog & SystemVerilog
- CHISEL HDL
- Transformers & LLMs
- Vector Databases & RAG
This project is intended for educational purposes.