Silicon crew challenge 4

UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_env.yaml

@@ -0,0 +1,84 @@
+uvmf:
+  benches:
+    "block_1" :
+      ## Specify the top-level block
+      top_env: "block_1"
+      clock_half_period: "5ns"
+      reset_assertion_level: "True"
+      reset_duration: "200ns"
+      active_passive: 
+        - bfm_name: "apb_master" 
+          value: "ACTIVE"
+        - bfm_name: "axi_master1" 
+          value: "ACTIVE"
+        - bfm_name: "axi_master2" 
+          value: "ACTIVE"
+        - bfm_name: "spi_slave" 
+          value: "PASSIVE"
+  environments:
+    "block_1" :
+      agents :
+        - name: "apb_master" 
+          type: "apb_m"
+          initiator_responder: "INITIATOR"
+
+        - name: "axi_master1"
+          type: "axi_m"
+          initiator_responder: "INITIATOR"
+
+        - name: "axi_master2"
+          type: "axi_m"
+          initiator_responder: "INITIATOR"
+
+        - name: "spi_slave"
+          type: "spi_s"
+          initiator_responder: "RESPONDER"
+
+      analysis_components :
+        - name: "block_1_pred"
+          type: "block_1_predictor"
+        - name: "block_1_sb"
+          type: "block_1_scoreboard"
+
+      analysis_ports :
+        - name: "apb_master_ap"
+          trans_type: "apb_m_transaction"
+          connected_to: "apb_master.monitored_ap"
+        - name: "axi_master1_ap"
+          trans_type: "axi_m_transaction"
+          connected_to: "axi_master1.monitored_ap"
+        - name: "axi_master2_ap"
+          trans_type: "axi_m_transaction"
+          connected_to: "axi_master2.monitored_ap"
+        - name: "spi_slave_ap"
+          trans_type: "spi_s_transaction"
+          connected_to: "spi_slave.monitored_ap"
+      #  - name: "block_1_ap1"
+      #    trans_type: "apb_m_transaction"
+      #    connected_to: "apb_master.monitored_ap"
+      #  - name: "block_1_ap2"
+      #    trans_type: "axi_m_transaction"
+      #    connected_to: "axi_master1.monitored_ap"
+      #  - name: "block_1_ap3"
+      #    trans_type: "axi_m_transaction"
+      #    connected_to: "axi_master2.monitored_ap"
+      #  - name: "block_2_ap1"
+      #    trans_type: "spi_s_transaction"
+      #    connected_to: "spi_slave.monitored_ap"
+
+      tlm_connections: 
+        - driver:   "spi_slave.monitored_ap"
+          receiver: "block_1_sb.spi_ae"
+        - driver:   "apb_master.monitored_ap"
+          receiver: "block_1_pred.apb_ae"
+        - driver:   "axi_master1.monitored_ap"
+          receiver: "block_1_pred.axi_1_ae"
+        - driver:   "axi_master2.monitored_ap"
+          receiver: "block_1_pred.axi_2_ae"
+        - driver:   "block_1_pred.pre_to_sco_ap"
+          receiver: "block_1_sb.sco_from_pre_ae"
+
+      config_vars :
+        - name: "has_scoreboard"
+          type : "bit"      
+          isrand : "False"

UVM_Framework/UVMF_2022.3/challenge_3/block_1/block1_util.yaml

@@ -0,0 +1,22 @@
+uvmf:
+  util_components:
+    block_1_predictor:
+      analysis_exports:
+      - name: apb_ae
+        type: 'apb_m_transaction'
+      - name: axi_1_ae
+        type: 'axi_m_transaction'
+      - name: axi_2_ae
+        type: 'axi_m_transaction'
+      analysis_ports:
+      - name: pre_to_sco_ap
+        type: 'spi_s_transaction'
+      existing_library_component: 'True'
+      type: predictor
+    block_1_scoreboard:
+      analysis_exports:
+      - name: spi_ae
+        type: 'spi_s_transaction'
+      - name: sco_from_pre_ae
+        type: 'spi_s_transaction'
+      type: scoreboard

UVM_Framework/UVMF_2022.3/challenge_3/block_1/block_1.csh

@@ -0,0 +1,7 @@
+# Setting the path for making "make cli" command works fine.
+
+setenv UVMF_HOME /hwetools/work_area/frontend/vinay_B7/UVMF/UVM_Framework/UVMF_2022.3/
+
+# This is the command to generate you block_1_level bench
+
+python ../../../UVMF_2022.3/scripts/yaml2uvmf.py ../intf/apb_m_intf.yaml ../intf/axi_m_intf.yaml ../intf/spi_s_intf.yaml ../block_1/block1_env.yaml ../block_1/block1_util.yaml

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.project

@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>block_1</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>net.sf.sveditor.core.SVProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>net.sf.sveditor.core.SVNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>verification_ip</name>
+			<type>2</type>
+			<locationURI>UVMF_VIP_LIBRARY_HOME</locationURI>
+		</link>
+	</linkedResources>
+	<variableList>
+		<variable>
+			<name>UVMF_VIP_LIBRARY_HOME</name>
+			<value>$%7BPARENT-2-PROJECT_LOC%7D/verification_ip</value>
+		</variable>
+	</variableList>
+</projectDescription>
+

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/.svproject

@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<svproject>
+  <defines/>
+  <includePaths/>
+  <buildPaths/>
+  <pluginPaths>
+    <pluginPath path="net.sf.sveditor.sv_builtin"/>
+  </pluginPaths>
+  <libraryPaths/>
+  <argFilePaths>
+    <argFilePath path="${project_loc}/block_1_sve.F"/>
+  </argFilePaths>
+  <sourceCollections/>
+  <projectRefs/>
+  <templatePaths/>
+</svproject>

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/block_1_sve.F

@@ -0,0 +1,29 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/apb_m_pkg/apb_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/axi_m_pkg/axi_m_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/spi_s_pkg/spi_s_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/block_1_env_pkg/block_1_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/block_1_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/block_1_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/block_1_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/docs/interfaces.csv

@@ -0,0 +1,16 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+apb_master, apb_m_driver_bfm apb_m_monitor_bfm, apb_m_transaction, apb_m_pkg_apb_master_BFM,
+axi_master1, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master1_BFM,
+axi_master2, axi_m_driver_bfm axi_m_monitor_bfm, axi_m_transaction, axi_m_pkg_axi_master2_BFM,
+spi_slave, spi_s_driver_bfm spi_s_monitor_bfm, spi_s_transaction, spi_s_pkg_spi_slave_BFM,
+

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/dut.compile

@@ -0,0 +1,6 @@
+
+# pragma uvmf custom dut_compile_info begin
+src:
+  - ./vhdl/vhdl_dut.vhd
+  - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.v

@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+   if (rst) begin
+     out_signal_o <= 0;
+     end 
+   else begin
+     out_signal_o <= ~in_signal;
+     end
+   end
+
+assign out_signal = out_signal_o;
+
+endmodule

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/verilog/verilog_dut.vinfo

@@ -0,0 +1 @@
+verilog_dut.v

UVM_Framework/UVMF_2022.3/challenge_3/block_1/uvmf_template_output/project_benches/block_1/rtl/vhdl/vhdl_dut.vhd

@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+   port ( clk : in std_logic ;
+          rst : in std_logic ;
+          in_signal : in std_logic ;
+          out_signal :out std_logic 
+        );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+   begin
+      P1: process
+            variable out_signal_o : std_logic;
+            begin
+               wait until clk'event and clk = '1';
+               out_signal_o := in_signal;
+               out_signal <= out_signal_o;
+     end process;
+   end rtl;