jtag env and bench yaml files

UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_sequence.sv

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+class add_in_fixed extends add_in_sequence_base;
+
+  function new(string name = "add_in_fixed");
+    super.new(name);
+  endfunction: new
+
+  task body();
+    req=add_in_transaction ::type_id::create("req");
+    start_item(req);
+    if(!req.randomize()) `uvm_fatal("SEQ", "add_in_fixed randomization failed")
+     req.a=5;
+     req.b=6;
+    finish_item(req);
+    `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+  endtask
+endclass

UVM_Framework/UVMF_2022.3/adder_test_cases/fixed_test.sv

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+`include "uvm_macros.svh"
+
+class add_fixed_test extends test_top;
+
+  `uvm_component_utils(add_fixed_test) 
+
+  function new(string name = "add_fixed_test", uvm_component parent = null );
+    super.new(name, parent);
+  endfunction : new
+
+  virtual function void build_phase(uvm_phase phase );
+    add_bench_sequence_base::type_id::set_type_override(add_fixed_sequence::get_type());
+    super.build_phase(phase);
+  endfunction : build_phase
+
+endclass : add_fixed_test

UVM_Framework/UVMF_2022.3/adder_test_cases/random_sequence.sv

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+`include "uvm_macros.svh"
+
+class add_random_sequence extends add_bench_sequence_base;
+
+  `uvm_object_utils(add_random_sequence) 
+
+  function new(string name = "add_random_sequence");
+    super.new(name);
+  endfunction : new
+
+  virtual task body();
+  add_random_seq = add_random_sequence#()::type_id::create("add_agent_random_seq");
+
+  add_agent_config.wait_for_reset();
+  add_agent_config.wait_for_num_clocks(10);
+
+  repeat (10) add_agent_random_seq.start(add_agent_sequencer);
+
+  add_agent_config.wait_for_num_clocks(10);    
+
+endtask
+
+endclass : ALU_random_sequence

UVM_Framework/UVMF_2022.3/adder_test_cases/random_test.sv

@@ -0,0 +1,16 @@
+`include "uvm_macros.svh"
+
+class add_random_test extends test_top;
+
+  `uvm_component_utils(add_random_test) 
+
+  function new(string name = "add_random_test", uvm_component parent = null );
+    super.new(name, parent);
+  endfunction : new
+
+  virtual function void build_phase(uvm_phase phase );
+    add_bench_sequence_base::type_id::set_type_override(add_random_sequence::get_type());
+    super.build_phase(phase);
+  endfunction : build_phase
+
+endclass : add_random_test

UVM_Framework/UVMF_2022.3/adder_test_cases/reset_sequence.sv

@@ -0,0 +1,17 @@
+class add_in_reset_sequence extends add_in_sequence_base;
+
+  function new(string name = "add_reset_sequence");
+    super.new(name);
+  endfunction: new
+
+  task body();
+    req=add_in_transaction ::type_id::create("req");
+    start_item(req);
+    if(!req.randomize()) `uvm_fatal("SEQ", "add_in_reset_sequence::body()-add_transaction randomization failed")
+     // req.reset=1;
+     req.op = rst_op;
+    finish_item(req);
+    `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+  endtask
+endclass

UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_1.sv

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+`include "uvm_macros.svh"
+
+class sequence_1_reset extends add_bench_sequence_base;
+
+
+  `uvm_object_utils(sequence_1_reset)
+
+  typedef add_in_reset_sequence add_in_reset_sequence_t;
+  add_in_reset_sequence_t add_in_reset_s;
+
+  function new(string name="sequence_1_reset");
+    super.new(name);
+  endfunction
+
+  virtual task body();
+   add_in_reset_s = add_in_reset_sequence#() ::type_id::create("add_in_reset_s"); 
+
+   add_in_reset_s.start(add_in_agent_sequencer);
+  endtask
+
+endclass

UVM_Framework/UVMF_2022.3/adder_test_cases/sequence_2.sv

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+`include "uvm_macros.svh"
+
+class sequence_2_fixed extends add_bench_sequence_base;
+
+
+  `uvm_object_utils(sequence_2_fixed)
+
+  typedef add_in_reset_sequence add_in_reset_sequence_t;
+  add_in_reset_sequence_t add_in_reset_s;
+
+  function new(string name="sequence_2_fixed");
+    super.new(name);
+  endfunction
+
+  virtual task body();
+   add_in_reset_s = add_in_reset_sequence#() ::type_id::create("add_in_reset_s"); 
+   add_in_fixed = add_in_fixed_sequence#() ::type_id::create("add_in_reset_s"); 
+
+   add_in_reset_s.start(add_in_agent_sequencer);
+   add_in_fixed.start(add_in_agent_sequencer);
+  endtask
+
+endclass

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.project

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+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>jtag</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>net.sf.sveditor.core.SVProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>net.sf.sveditor.core.SVNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>verification_ip</name>
+			<type>2</type>
+			<locationURI>UVMF_VIP_LIBRARY_HOME</locationURI>
+		</link>
+	</linkedResources>
+	<variableList>
+		<variable>
+			<name>UVMF_VIP_LIBRARY_HOME</name>
+			<value>$%7BPARENT-2-PROJECT_LOC%7D/verification_ip</value>
+		</variable>
+	</variableList>
+</projectDescription>
+

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/.svproject

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<svproject>
+  <defines/>
+  <includePaths/>
+  <buildPaths/>
+  <pluginPaths>
+    <pluginPath path="net.sf.sveditor.sv_builtin"/>
+  </pluginPaths>
+  <libraryPaths/>
+  <argFilePaths>
+    <argFilePath path="${project_loc}/jtag_sve.F"/>
+  </argFilePaths>
+  <sourceCollections/>
+  <projectRefs/>
+  <templatePaths/>
+</svproject>

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/docs/interfaces.csv

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+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+,
+Interface Description, Interface Type, Interface Transaction, Interface Name,
+jtag_in, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_in_BFM,
+jtag_out, jtag_driver_bfm jtag_monitor_bfm, jtag_transaction, jtag_pkg_jtag_out_BFM,
+

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/jtag_sve.F

@@ -0,0 +1,27 @@
+
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
+// BFM Files
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/jtag_pkg/jtag_pkg_sve.F
+
+// Environment Files
+-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/jtag_env_pkg/jtag_env_pkg_sve.F
+
+// Bench Files
++incdir+./tb/tests
+./tb/tests/jtag_tests_pkg.sv
+
++incdir+./tb/sequences
+./tb/sequences/jtag_sequences_pkg.sv
+
++incdir+./tb/parameters
+./tb/parameters/jtag_parameters_pkg.sv
+
+./tb/testbench/hdl_top.sv
+./tb/testbench/hvl_top.sv
+

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/dut.compile

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+
+# pragma uvmf custom dut_compile_info begin
+src:
+  - ./vhdl/vhdl_dut.vhd
+  - ./verilog/verilog_dut.v
+# pragma uvmf custom dut_compile_info end

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.v

@@ -0,0 +1,21 @@
+module verilog_dut(clk, rst, in_signal, out_signal);
+
+input clk;
+input rst;
+input in_signal;
+output out_signal;
+
+reg out_signal_o;
+
+always @(posedge clk) begin
+   if (rst) begin
+     out_signal_o <= 0;
+     end 
+   else begin
+     out_signal_o <= ~in_signal;
+     end
+   end
+
+assign out_signal = out_signal_o;
+
+endmodule

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/verilog/verilog_dut.vinfo

@@ -0,0 +1 @@
+verilog_dut.v

UVM_Framework/UVMF_2022.3/challenge2_gen_env_bench_for_diag/challenge_2_Generated_output/project_benches/jtag/rtl/vhdl/vhdl_dut.vhd

@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity vhdl_dut is
+   port ( clk : in std_logic ;
+          rst : in std_logic ;
+          in_signal : in std_logic ;
+          out_signal :out std_logic 
+        );
+end vhdl_dut;
+
+architecture rtl of vhdl_dut is
+   begin
+      P1: process
+            variable out_signal_o : std_logic;
+            begin
+               wait until clk'event and clk = '1';
+               out_signal_o := in_signal;
+               out_signal <= out_signal_o;
+     end process;
+   end rtl;