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Adder Design Code #9

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690f96c
dut
Dec 20, 2022
e8cef2e
new
Dec 20, 2022
80b8398
deleted
Dec 23, 2022
f3a25a1
challenge 3
Dec 23, 2022
3b6e87c
interfaces
Dec 23, 2022
1c93cad
hi
Dec 23, 2022
dfa4cfc
Adding wb intf yaml files
VINUTHNA-SRI Dec 23, 2022
266ce8a
apb_interface.yaml
Dec 23, 2022
167e985
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
Dec 23, 2022
e4b9235
template files edited
Dec 23, 2022
a455f03
initial for merge
Dec 23, 2022
5e5700a
Adding intfs
VINUTHNA-SRI Dec 23, 2022
95007c4
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
VINUTHNA-SRI Dec 23, 2022
7e1b0b1
block_a modified
vineethkumarv Dec 23, 2022
4fc86d6
interface template edited
vineethkumarv Dec 23, 2022
e75fa86
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
Dec 23, 2022
ff8c27e
block_a
Dec 23, 2022
1951f63
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
Dec 23, 2022
1ca56bd
axi master and slave interfaces
Dec 23, 2022
8f4821a
block_a
Dec 23, 2022
a4c3263
predictors and scoreboards
Dec 24, 2022
c94d67e
wb
VINUTHNA-SRI Dec 24, 2022
fb13d24
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
VINUTHNA-SRI Dec 24, 2022
b5d5875
added block2 and few edits
vineethkumarv Dec 24, 2022
0a1f52f
directory names changed
Dec 24, 2022
0e122bf
Adding subsytem env and utils
VINUTHNA-SRI Dec 24, 2022
6aa90c5
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
VINUTHNA-SRI Dec 24, 2022
bac99ae
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
Dec 24, 2022
4708198
subsytem files
VINUTHNA-SRI Dec 24, 2022
b0a2132
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
VINUTHNA-SRI Dec 24, 2022
1d26ca7
axi iscompare
Dec 24, 2022
f3d3980
Merge branch 'B7_Team_BJT' of github.com:muneeb-mbytes/UVMF into B7_T…
Dec 24, 2022
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99 changes: 99 additions & 0 deletions UVM_Framework/UVMF_2022.3/challenge_3/apb_m_intf.yaml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,99 @@
uvmf:
interfaces:
"apb":
clock: "pclk"
reset: "presetn"
veloce_ready: "True"
reset_assertion_level: 'False'
parameters:
- name: "APB_ADDR_WIDTH"
type: "int"
value: '32'
- name: "APB_DATA_WIDTH"
type: "int"
value: '32'
- name: "STRB_LEN"
type: "int"
value: "APB_ADDR_WIDTH/8"
ports:
- dir: "output"
name: "psel"
reset_value: '''b0'
width: '16'
- dir: "output"
name: "penable"
reset_value: '''b0'
width: '1'
- dir: "output"
name: "paddr"
reset_value: '''b0'
width: "APB_ADDR_WIDTH"
- dir: "output"
name: "pwdata"
reset_value: '''b0'
width: "APB_DATA_WIDTH"
- dir: "output"
name: "pwrite"
reset_value: '''b0'
width: '1'
- dir: "output"
name: "pstrb"
reset_value: '''b0'
width: 'STRB_LEN'
- dir: "output"
name: "pprot"
reset_value: '''b0'
width: '3'
- dir: "input"
name: "prdata"
reset_value: '''b0'
width: "APB_DATA_WIDTH"
- dir: "input"
name: "pready"
reset_value: '0'
width: '1'
- dir: "input"
name: "pslverr"
reset_value: '0'
width: '1'
transaction_vars:
- iscompare: 'False'
isrand: 'True'
name: "psel"
type: "bit"
- iscompare: 'True'
isrand: 'True'
name: "penable"
type: "bit"
- iscompare: 'True'
isrand: 'True'
name: "paddr"
type: "bit [APB_ADDR_WIDTH-1:0]"
- iscompare: 'True'
isrand: 'True'
name: "pwdata"
type: "bit [APB_DATA_WIDTH-1:0]"
- iscompare: 'True'
isrand: 'True'
name: "pwrite"
type: "bit"
- iscompare: 'True'
isrand: 'True'
name: "pstrb"
type: "bit [STRB_LEN:0]"
- iscompare: 'True'
isrand: 'True'
name: "pprot"
type: "bit [3:0]"
- iscompare: 'True'
isrand: 'False'
name: "prdata"
type: "APB_DATA_WIDTH"
- iscompare: 'True'
isrand: 'False'
name: "pready"
type: "bit"
- iscompare: 'True'
isrand: 'False'
name: "pslverr"
type: "bit"
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