Regenerate missing or stale Verilog when linking

[nanavati]

Verilog linking already loaded the design's .ba hierarchy and discarded it ("XXX Until we allow re-generation of Verilog files"). Now the link regenerates any module .v that is missing or older than its .ba, reuses the rest (reported like Bluesim's object reuse), and passes the module .v files to the simulator explicitly. A .v given on the command line is the user's to provide and is never regenerated; file arguments can be glob patterns (bsc forwards them to the simulator's shell unexpanded), so module names are matched against the patterns -- "*.v" keeps its longstanding meaning of "the user provides every module". When no .ba hierarchy can be found, the link warns (S0099) and uses the .v files as found, as before. This makes a link self-sufficient regardless of which subset of the design was pre-generated with -c: -c is point codegen, link is the closure.

Rather than adding a third variant of generated-file staleness checking, the timestamp conventions move to a shared StaleUtils (missing product is never fresh, equal times are fresh), used by the -u check, Bluesim object reuse, and the new VFileUtils; the checks now agree by construction, and each keeps only its own validity details (options descriptor for Bluesim objects, .ba usability for -u).