feat(inner_jib_top): full integration + sum_ints end-to-end test passing

[marcos-mendez]

Sprint C complete. src/inner_jib_top.sv wires the upstream RISC-V core through MAST's AXI4 subsystem to an internal SRAM, with a cocotb test that runs sum_ints.asm end-to-end and verifies the expected output sequence.

What this proves

upstream core.sv -> core_axi4_adapter -> axi4_master_simple -> axi4_mem_model

A real RISC-V program (mast/examples/direct/sum_ints.asm, the classic verigpu sum-of-integers benchmark) is loaded into the mem model via the new back-door loader port, then the core is released to fetch instructions through AXI4 and execute them. Every output value the core emits via its out/outen ports is captured and the captured sequence is asserted to equal the hand-traced expected sequence.

TESTS=2 PASS=2 FAIL=0 SKIP=0
  test_reset                       PASS    90 ns
  test_sum_ints_runs_and_halts     PASS  2530 ns sim time

This is the first program of any kind running on PopSolutions silicon-equivalent hardware in simulation. Every subsequent program lands on the same path.

Dependencies

• Depends on popsolutions/MAST#8 (mem_model back-door loader port). The MAST submodule is temporarily pinned to MAST's feat/mem-loader branch (commit c12a6a5); it will be bumped to MAST main HEAD after MAST#8 merges. Until MAST#8 merges, CI on this PR will pass because the submodule checks out the branch directly.

Files

• src/inner_jib_top.sv — top-level integration module
• verif/inner_jib_top/Makefile — cocotb makefile referencing all upstream + MAST sources
• verif/inner_jib_top/test_inner_jib_top.py — 2 cocotb tests
• verif/inner_jib_top/fixtures/sum_ints.hex — pre-assembled hex (20 instructions)
• .github/workflows/ci.yml — first CI workflow for InnerJib7EA, mirrors MAST's pattern with submodule init
• README.md — status badge, local run instructions
• .gitignore — verif outputs

Closes

• [hw] inner_jib_top.sv — top-level integration (1 CU + AXI4 + axi4_mem_model + UART) #4 (top-level integration)

Self-review

Will be added as a PR comment after CI goes green and the code-reviewer agent runs.

[marcos-mendez]

Self-review (code-reviewer agent, 2026-05-05)

Per MAST/GOVERNANCE.md self-review bridge.

Severity	Count	Status
CRITICAL	0	—
HIGH	0	—
HIGH-adjacent	1	Upstream issue (regs[1..31] not zeroed in core.sv reset). Inherited from upstream VeriGPU; not introduced by this PR; not blocking. Will file separately as an upstream issue.
MEDIUM	2	Both addressed in 0b1d04b1
LOW	0	—

MEDIUM 1 — addressed

Fixture regeneration recipe missing. sum_ints.hex was checked in without documenting the exact command to regenerate it. Fix: added verif/inner_jib_top/fixtures/README.md with the assembler invocation, the hand-traced expected output, and the rationale for checking the hex in versus regenerating in CI.

MEDIUM 2 — addressed

Loader-to-core start timing assumption. Documented in the fixture README via the rationale paragraph. A dedicated inline comment in the test loop can land in a small doc-only follow-up PR.

Cross-cutting risk — MAST submodule branch pin

The submodule was pinned to MAST's feat/mem-loader branch. After MAST PR #8's self-review fixes landed, this commit bumps the pin to include those fixes (still on the same branch — PR #8 hasn't merged yet). When PR #8 merges, a small follow-up commit will bump the pin to a MAST-main-reachable SHA.

Upstream issue noted (not blocking this PR)

mast/src/core.sv does not zero regs[1..31] in its async reset path. For sum_ints this is benign because the program writes both registers (x1, x2) before reading them. Programs that read an uninitialized register will see X-propagation. Will file as upstream issue with verigpu maintainers rather than fix locally.

Verdict from this self-review pass

APPROVE-WITH-NITS for merge. No CRITICAL or HIGH findings. Per GOVERNANCE.md "No AI self-merge" clause, the merge button is yours, Marcos. This PR depends on MAST PR #8; merge MAST #8 first, then this one. Suggested sequence:

# After CI on both PRs is green:
gh pr merge 8 --repo popsolutions/MAST --squash
gh pr merge 7 --repo popsolutions/InnerJib7EA --squash

(After merging InnerJib7EA #7, the submodule will still point at MAST's feat/mem-loader branch HEAD; a tiny follow-up PR can bump it to MAST main HEAD for cleanliness.)