Implement pseudorandom number generator#14
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JesseDeMeulemeester wants to merge 5 commits intoproteus-core:mainfrom
Open
Implement pseudorandom number generator#14JesseDeMeulemeester wants to merge 5 commits intoproteus-core:mainfrom
JesseDeMeulemeester wants to merge 5 commits intoproteus-core:mainfrom
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Co-authored-by: Quinten Norga <43999019+qnorga1@users.noreply.github.com>
* Replaced AES core with Bivium core for more efficient random number generation. This reduces area usage and improves performance to 1 random number per clock cycle. * Refactored the connection between the RngCore and the RngFifos to remove unnecessary buffers
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Thank you and sorry for the late response! If I understand correctly, the implementation has changed since you wrote the original message, could you update this so that it can serve as a good reference for what was merged? |
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Yes, we swapped out the AES core with Bivium, which offers better throughput/area. And we also fixed some of the minor issues. I have updated the main comment. |
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This PR implements a pseudorandom number generator. It provides an
RngServicethat can be called in any component that requires random numbers. We use unrolled Bivium [1] to generate a continuous random stream, where the Bivium core produces one 32-bit (64-bit) random value every cycle for RV32 (RV64). To improve latency, each component that requires random numbers holds a small buffer to hold the random values. The RNG core itself is shared between all components that register a buffer with the RNG component. The RNG component will fill these buffers with the values produced by the core in Round Robin fashion, and can provide up to one random number every clock cycle.Initialization
The (80-bit) key for the Bivium core can be set at runtime through CSRs. By default, the RNG component will not generate any random numbers until the seed has been updated. This behavior can be disabled by setting the
allowUninitializedRngflag when initializing the RNG. The RNG core will then use a hard-coded key instead.The RNG component can also be disabled through a control CSR. If the disable bit is set, timings will remain the same, but the RNG component will only return zero.
The different CSRs that are used by this component are as follows:
RNG Control CSR
Note that both of these actions can only be performed once, i.e., the RNG component will only respond the first time these bits are set.
Usage
The usage is very similar to CSRs:
You add the RNG plugin (note that this plugin has to be added after any other plugin that requires it):
You register a buffer with the RngService:
By default, the RngFifo has a depth of 2, but this can be changed by setting the
queueDepthparameter when instantiating the RngFifo.You can then get random numbers from this buffer: