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Merged
yvantor merged 1 commit into from
Nov 27, 2025
Merged

Make input clocks parametric on chosen configuration. #64

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42 changes: 17 additions & 25 deletions hw/astral_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,6 @@

// clock signals
logic ref_clk;
// generated clocks
logic host_clk, periph_clk, alt_clk, rt_clk;

// secure boot mode signal
logic secure_boot;
Expand Down Expand Up @@ -298,14 +296,6 @@
// GPI0 22-31 remain unconnected
assign gpio_in_s[31:22] = '0;

// soc2pad
// clocks
assign st_soc2pad_signals.periph.fll_host_clk_o = host_clk;
assign st_soc2pad_signals.periph.fll_periph_clk_o = periph_clk;
assign st_soc2pad_signals.periph.fll_alt_clk_o = alt_clk;
assign st_soc2pad_signals.periph.fll_rt_clk_o = rt_clk;


// soc2pad
// uart-- carfield itf
// spi
Expand Down Expand Up @@ -361,7 +351,6 @@
//////////////////////
// Clock generation //
//////////////////////

logic[carfield_pkg::NumFll-1:0] clk_fll_out;
logic[carfield_pkg::NumFll-1:0] clk_fll_e;
logic[carfield_pkg::NumFll-1:0] fll_lock;
Expand All @@ -372,29 +361,29 @@
logic[carfield_pkg::NumFll-1:0] fll_scan_out;
logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_in;
logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_out;
logic[carfield_pkg::NumFll-1:0] domain_clk;

// ref_clk
assign ref_clk = st_pad2soc_signals.periph.ref_clk_i;
// power on reset
assign pwr_on_rst_n = st_pad2soc_signals.periph.pwr_on_rst_ni;

assign host_clk = clk_fll_out[0];
assign periph_clk = clk_fll_out[1];
assign alt_clk = clk_fll_out[2];
assign secd_clk = clk_fll_out[3];
assign clk_fll_e = '{default: 1'b1};

clk_int_div_static #(
.DIV_VALUE ( 100 ),
.ENABLE_CLOCK_IN_RESET( 1'b1 )
) i_rt_clk_div (
.clk_i ( clk_fll_out[4] ),
.rst_ni ( pwr_on_rst_n ),
.en_i ( 1'b1 ),
.test_mode_en_i ( 1'b0 ),
.clk_o ( rt_clk )
.clk_i ( clk_fll_out[carfield_pkg::RtClockIdx]),
.rst_ni ( pwr_on_rst_n ),
.en_i ( 1'b1 ),
.test_mode_en_i ( 1'b0 ),
.clk_o ( domain_clk[carfield_pkg::RtClockIdx] )
);

for (genvar i = 1; i < carfield_pkg::NumFll; i++)
assign domain_clk[i] = clk_fll_out[i];

assign fll_pwd = '{default: 1'b0};
assign fll_test_mode = '{default: 1'b0};
assign fll_scan_e = '{default: 1'b0};
Expand Down Expand Up @@ -477,6 +466,13 @@
assign dummy_rsp.rdata = 'hCACABABE;
`endif

// soc2pad
// clocks
assign st_soc2pad_signals.periph.fll_rt_clk_o = clk_fll_out[carfield_pkg::RtClockIdx];
assign st_soc2pad_signals.periph.fll_host_clk_o = clk_fll_out[carfield_pkg::HostClockIdx];
assign st_soc2pad_signals.periph.fll_alt_clk_o = clk_fll_out [carfield_pkg::CarfieldClockIdx.AltClockIdx];

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Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]" location:{path:"hw/astral_wrap.sv" range:{start:{line:473 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

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Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]" location:{path:"hw/astral_wrap.sv" range:{start:{line:473 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
assign st_soc2pad_signals.periph.fll_periph_clk_o = clk_fll_out [carfield_pkg::CarfieldClockIdx.PeriphClockIdx];

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Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/astral_wrap.sv" range:{start:{line:474 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

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Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/astral_wrap.sv" range:{start:{line:474 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

//////////////////
// Carfield SoC //
//////////////////
Expand All @@ -488,11 +484,7 @@
.reg_req_t ( carfield_reg_req_t ),
.reg_rsp_t ( carfield_reg_rsp_t )
) i_dut (
.host_clk_i ( host_clk ),
.periph_clk_i ( periph_clk ),
.alt_clk_i ( alt_clk ),
.secd_clk_i ( secd_clk ),
.rt_clk_i ( rt_clk ),
.domain_clk_i ( domain_clk[carfield_pkg::NumFll-1:0] ),
.pwr_on_rst_ni ( pwr_on_rst_n ),
.test_mode_i ( '0 ),
.boot_mode_i ( bootmode_host_s[1:0] ),
Expand Down
77 changes: 37 additions & 40 deletions hw/carfield.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -37,16 +37,7 @@ module carfield
localparam int unsigned SlinkNumChan = cheshire_pkg::SlinkNumChan,
localparam int unsigned SlinkNumLanes = cheshire_pkg::SlinkNumLanes
) (
// host clock
input logic host_clk_i,
// peripheral clock
input logic periph_clk_i,
// accelerator and island clock
input logic alt_clk_i,
// secure domain clock
input logic secd_clk_i,
// external reference clock for timers (CLINT, islands)
input logic rt_clk_i,
input logic [carfield_pkg::NumFll-1:0] domain_clk_i,

input logic pwr_on_rst_ni,

Expand Down Expand Up @@ -183,6 +174,8 @@ module carfield
`CHESHIRE_TYPEDEF_ALL(carfield_, Cfg)

// Clocking and reset strategy
logic rt_clk;
logic host_clk;
logic periph_rst_n;
logic safety_rst_n;
logic security_rst_n;
Expand Down Expand Up @@ -217,6 +210,10 @@ logic [4:0] car_wdt_intrs;
logic car_can_intr;
logic car_eth_rx_intr;

// Assign clocks to each domain
assign rt_clk = domain_clk_i[carfield_pkg::RtClockIdx];
assign host_clk = domain_clk_i[carfield_pkg::HostClockIdx];

// Carfield peripheral interrupts
// Propagate edge-triggered interrupts between periph and host clock domains

Expand All @@ -226,7 +223,7 @@ for (genvar i=0; i < CarfieldNumAdvTimerIntrs; i++) begin : gen_sync_adv_timer_i
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
.edge_i ( car_adv_timer_intrs[i] ),
.clk_rx_i ( host_clk_i ),
.clk_rx_i ( host_clk ),
.rstn_rx_i ( host_pwr_on_rst_n ),
.edge_o ( car_adv_timer_intrs_sync[i] )
);
Expand All @@ -237,7 +234,7 @@ for (genvar i=0; i < CarfieldNumAdvTimerEvents; i++) begin : gen_sync_adv_timer_
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
.edge_i ( car_adv_timer_events[i] ),
.clk_rx_i ( host_clk_i ),
.clk_rx_i ( host_clk ),
.rstn_rx_i ( host_pwr_on_rst_n ),
.edge_o ( car_adv_timer_events_sync[i] )
);
Expand All @@ -248,7 +245,7 @@ edge_propagator i_sync_sys_timer_lo_intr (
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
.edge_i ( car_sys_timer_lo_intr ),
.clk_rx_i ( host_clk_i ),
.clk_rx_i ( host_clk ),
.rstn_rx_i ( host_pwr_on_rst_n ),
.edge_o ( car_sys_timer_lo_intr_sync )
);
Expand All @@ -257,7 +254,7 @@ edge_propagator i_sync_sys_timer_hi_intr (
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
.edge_i ( car_sys_timer_hi_intr ),
.clk_rx_i ( host_clk_i ),
.clk_rx_i ( host_clk ),
.rstn_rx_i ( host_pwr_on_rst_n ),
.edge_o ( car_sys_timer_hi_intr_sync )
);
Expand Down Expand Up @@ -492,7 +489,7 @@ end
// hard reset is:
// periph (periph_clk_i) and accelerators (alt_clk_i)
//
// The host is statically always assigned to host_clk_i.
// The host is statically always assigned to host_clk.
//
// Furthermore we have six reset domains:
// host (contained in host clock domain, POR only, no SW reset)
Expand Down Expand Up @@ -541,12 +538,12 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux
clk_mux_glitch_free #(
.NUM_INPUTS(carfield_pkg::NumFll-1)
) i_clk_mux (
.clks_i ( {secd_clk_i, periph_clk_i, alt_clk_i, host_clk_i} ),
.test_clk_i ( 1'b0 ),
.test_en_i ( 1'b0 ),
.async_rstn_i ( host_pwr_on_rst_n ),
.async_sel_i ( domain_clk_sel[i] ),
.clk_o ( domain_clk[i] )
.clks_i ( domain_clk_i[carfield_pkg::NumFll-1:1] ),
.test_clk_i ( 1'b0 ),
.test_en_i ( 1'b0 ),
.async_rstn_i ( host_pwr_on_rst_n ),
.async_sel_i ( domain_clk_sel[i] ),
.clk_o ( domain_clk[i] )
);

// The register file does not support back pressure directly. I.e the hardware side cannot tell
Expand All @@ -558,7 +555,7 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux
lossy_valid_to_stream #(
.T(domain_clk_div_value_t)
) i_decouple (
.clk_i ( host_clk_i ), // Connected to host clock since the soc_ctr
.clk_i ( host_clk ), // Connected to host clock since the soc_ctr
// regs are clocked with it
.rst_ni ( host_pwr_on_rst_n ), // See above
.valid_i ( domain_clk_div_changed[i] ),
Expand All @@ -574,7 +571,7 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux
.T(domain_clk_div_value_t)
) i_cdc (
.src_rst_ni ( host_pwr_on_rst_n ),
.src_clk_i ( host_clk_i ),
.src_clk_i ( host_clk ),
.src_data_i ( domain_clk_div_value_decoupled[i] ),
.src_valid_i ( domain_clk_div_decoupled_valid[i] ),
.src_ready_o ( domain_clk_div_decoupled_ready[i] ),
Expand Down Expand Up @@ -608,7 +605,7 @@ end
// Reset generation for power-on reset for host domain. For the other domain we
// get this from carfield_rstgen
rstgen i_host_rstgen (
.clk_i (host_clk_i),
.clk_i (host_clk),
.rst_ni (pwr_on_rst_ni),
.test_mode_i,
.rst_no (host_pwr_on_rst_n),
Expand Down Expand Up @@ -666,7 +663,7 @@ for (genvar i=0; i<NumSyncRegSlv; i++ ) begin : gen_chs_ext_reg_cut
.req_t ( carfield_reg_req_t ),
.rsp_t ( carfield_reg_rsp_t )
) i_chs_sync_ext_reg_cut (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.src_req_i ( ext_reg_req ),
.src_rsp_o ( ext_reg_rsp ),
Expand All @@ -685,7 +682,7 @@ carfield_reg_top #(
.reg_req_t(carfield_reg_req_t),
.reg_rsp_t(carfield_reg_rsp_t)
) i_carfield_reg_top (
.clk_i (host_clk_i),
.clk_i (host_clk),
.rst_ni (host_pwr_on_rst_n),
.reg_req_i(ext_reg_req_cut[PcrsIdx]),
.reg_rsp_o(ext_reg_rsp_cut[PcrsIdx]),
Expand Down Expand Up @@ -778,11 +775,11 @@ cheshire_wrap #(
`else
cheshire i_cheshire_wrap (
`endif
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.test_mode_i ,
.boot_mode_i ,
.rtc_i ( rt_clk_i ),
.rtc_i ( rt_clk ),
// External AXI LLC (DRAM) port
.axi_llc_isolate_i ( hyper_isolate_req ),
.axi_llc_isolated_o ( hyper_isolated_rsp ),
Expand Down Expand Up @@ -1149,7 +1146,7 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island
// interrupt lines, see `carfield_pkg.sv`). Other interrupt lines are level-triggered.
for (genvar i = 0; i < CarfieldNumTimerIntrs; i++) begin : gen_sync_safed_edge_triggered_intrs
edge_propagator i_sync_safed_edge_triggered_intrs (
.clk_tx_i ( host_clk_i ),
.clk_tx_i ( host_clk ),
.rstn_tx_i ( host_pwr_on_rst_n ),
.edge_i ( safed_edge_triggered_intrs[i] ),
.clk_rx_i ( safety_clk ),
Expand Down Expand Up @@ -1264,7 +1261,7 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island
safety_island i_safety_island_wrap (
`endif
.clk_i ( safety_clk ),
.ref_clk_i ( rt_clk_i ),
.ref_clk_i ( rt_clk ),
.rst_ni ( safety_rst_n ),
.pwr_on_rst_ni ( safety_pwr_on_rst_n ),
.test_enable_i ( test_mode_i ),
Expand Down Expand Up @@ -1441,7 +1438,7 @@ localparam pulp_cluster_package::pulp_cluster_cfg_t PulpClusterCfg = '{
.clk_i ( pulp_clk ),
.rst_ni ( pulp_rst_n ),
.pwr_on_rst_ni ( pulp_pwr_on_rst_n ),
.ref_clk_i ( rt_clk_i ),
.ref_clk_i ( rt_clk ),
.pmu_mem_pwdn_i ( '0 ),
.base_addr_i ( CarfieldIslandsCfg.pulp.base[31:28] ),
.test_mode_i ( test_mode_i ),
Expand Down Expand Up @@ -1783,7 +1780,7 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem
security_island i_security_island (
`endif
.clk_i ( security_clk ),
.clk_ref_i ( rt_clk_i ),
.clk_ref_i ( rt_clk ),
.rst_ni ( security_rst_n ),
.pwr_on_rst_ni ( security_pwr_on_rst_n ),
.fetch_en_i ( car_regs_reg2hw.security_island_fetch_enable ),
Expand Down Expand Up @@ -1876,7 +1873,7 @@ axi_cut #(
.axi_req_t ( carfield_axi_slv_req_t ),
.axi_resp_t ( carfield_axi_slv_rsp_t )
) i_cut_pre_amo_mbox (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.slv_req_i ( axi_mbox_req ),
.slv_resp_o ( axi_mbox_rsp ),
Expand All @@ -1902,7 +1899,7 @@ axi_riscv_atomics_structs #(
.axi_req_t ( carfield_axi_slv_req_t ),
.axi_rsp_t ( carfield_axi_slv_rsp_t )
) i_atomics_mbox (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.axi_slv_req_i ( axi_pre_amo_cut_mbox_req ),
.axi_slv_rsp_o ( axi_pre_amo_cut_mbox_rsp ),
Expand All @@ -1921,7 +1918,7 @@ axi_cut #(
.axi_req_t ( carfield_axi_slv_req_t ),
.axi_resp_t ( carfield_axi_slv_rsp_t )
) i_cut_post_amo_mbox (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.slv_req_i ( axi_amo_mbox_req ),
.slv_resp_o ( axi_amo_mbox_rsp ),
Expand All @@ -1944,7 +1941,7 @@ axi_to_reg_v2 #(
.reg_req_t ( carfield_reg_req_t ),
.reg_rsp_t ( carfield_reg_rsp_t )
) i_axi_to_reg_v2_mbox (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.axi_req_i ( axi_post_amo_cut_mbox_req ),
.axi_rsp_o ( axi_post_amo_cut_mbox_rsp ),
Expand All @@ -1959,7 +1956,7 @@ mailbox_unit #(
.reg_rsp_t( carfield_reg_rsp_t ),
.NumMbox ( NumMailboxes )
) i_mailbox_unit (
.clk_i ( host_clk_i ),
.clk_i ( host_clk ),
.rst_ni ( host_pwr_on_rst_n ),
.reg_req_i ( reg_mbox_req ),
.reg_rsp_o ( reg_mbox_rsp ),
Expand Down Expand Up @@ -2330,7 +2327,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care...
.PRDATA ( apb_mst_rsp[SystemTimerIdx].prdata ),
.PREADY ( apb_mst_rsp[SystemTimerIdx].pready ),
.PSLVERR ( apb_mst_rsp[SystemTimerIdx].pslverr ),
.ref_clk_i ( rt_clk_i ),
.ref_clk_i ( rt_clk ),
.event_lo_i ( '0 ),
.event_hi_i ( '0 ),
.irq_lo_o ( car_sys_timer_lo_intr ),
Expand All @@ -2354,7 +2351,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care...
.PRDATA ( apb_mst_rsp[AdvancedTimerIdx].prdata ),
.PREADY ( apb_mst_rsp[AdvancedTimerIdx].pready ),
.PSLVERR ( apb_mst_rsp[AdvancedTimerIdx].pslverr ),
.low_speed_clk_i ( rt_clk_i ),
.low_speed_clk_i ( rt_clk ),
.ext_sig_i ( '0 /* TODO connect me */ ),
.events_o ( car_adv_timer_events ),
.ch_0_o ( car_adv_timer_intrs ),
Expand Down Expand Up @@ -2419,7 +2416,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care...
aon_timer i_watchdog_timer (
.clk_i ( periph_clk ),
.rst_ni ( periph_pwr_on_rst_n ),
.clk_aon_i ( rt_clk_i ),
.clk_aon_i ( rt_clk ),
.rst_aon_ni ( periph_pwr_on_rst_n ),
.tl_i ( tl_wdt_req ),
.tl_o ( tl_wdt_rsp ),
Expand Down
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