Skip to content

Hook up the error signals in the L0 cache #30

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
colluca merged 1 commit into from
Jul 28, 2025
Merged

Hook up the error signals in the L0 cache #30

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/snitch_icache_handler.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,7 @@ module snitch_icache_handler #(
if (hit_valid) begin
out_rsp_ready_o = 0;
in_rsp_data_o = hit_data;
in_rsp_error_o = 0;
in_rsp_error_o = hit_error;
in_rsp_id_o = hit_id;
in_rsp_valid_o = 1;
hit_ready = in_rsp_ready_i;
Expand Down
7 changes: 5 additions & 2 deletions src/snitch_icache_l0.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ module snitch_icache_l0
typedef struct packed {
logic [CFG.L0_TAG_WIDTH-1:0] tag;
logic vld;
logic err;
} tag_t;

logic [CFG.L0_TAG_WIDTH-1:0] addr_tag, addr_tag_prefetch, addr_tag_prefetch_req;
Expand Down Expand Up @@ -150,6 +151,7 @@ module snitch_icache_l0
if (!rst_ni) begin
tag[i].vld <= 0;
tag[i].tag <= 0;
tag[i].err <= 0;
end else begin
if (evict_strb[i]) begin
tag[i].vld <= 1'b0;
Expand All @@ -158,6 +160,7 @@ module snitch_icache_l0
tag[i].vld <= 1'b0;
end else if (validate_strb[i]) begin
tag[i].vld <= 1'b1;
tag[i].err <= out_rsp_error_i;
end
end
end
Expand Down Expand Up @@ -193,8 +196,10 @@ module snitch_icache_l0
logic [CFG.LINE_WIDTH-1:0] ins_data;
always_comb begin : data_muxer
ins_data = '0;
in_error_o = 1'b0;
for (int unsigned i = 0; i < CFG.L0_LINE_COUNT; i++) begin
ins_data |= {CFG.LINE_WIDTH{hit[i]}} & data[i];
in_error_o |= hit[i] & tag[i].err;
end
in_data_o = CFG.FETCH_DW'(
ins_data >> (in_addr_i[CFG.LINE_ALIGN-1:CFG.FETCH_ALIGN] * CFG.FETCH_DW)
Expand Down Expand Up @@ -296,8 +301,6 @@ module snitch_icache_l0

assign out_rsp_ready_o = 1'b1;

assign in_error_o = '0;

assign out_req_addr_o = out_req.addr;
assign out_req_id_o = CFG.ID_WIDTH'(1'b1 << {L0_ID, out_req.is_prefetch});

Expand Down