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Add support for fractional priority in arbiter#76

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FrancescoConti wants to merge 1 commit intosmazzola/veriffrom
fc/fractional-qos-arbiter
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Add support for fractional priority in arbiter#76
FrancescoConti wants to merge 1 commit intosmazzola/veriffrom
fc/fractional-qos-arbiter

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Previously, HCI supported QoS by switching to the low-priority chan for 1 stall-cycle out of N, where N-1 was specified as the low_prio_max_stall configuration from a CSR in the system.
This commit changes the mechanism in a more flexible fractional priority. The counter has two configuration params (8-bit), both from CSRs: priority_cnt_numerator and priority_cnt_denominator. The former is the same as low_prio_max_stall, i.e., the number of stall-cycles the arbiter spends prioritizing the high-priority side. The latter is the total number of stall cycles after which the counter is cleared, meaning that the arbiter will spend priority_cnt_denominator-priority_cnt_numerator stall-cycles prioritizing the low-priority side.
In other words, the arbiter will dedicate a fraction numerator/denominator of the available bandwidth (on average) to the high priority side.

Hardware-wise the change is minimal, touching only how the counter works and the CSRs.

Previously, HCI supported QoS by switching to the low-priority chan
for 1 stall-cycle out of N, where N-1 was specified as the low_prio_max_stall
configuration from a CSR in the system.
This commit changes the mechanism in a more flexible fractional priority.
The counter has two configuration params (8-bit), both from CSRs:
priority_cnt_numerator and priority_cnt_denominator. The former is the
same as low_prio_max_stall, i.e., the number of stall-cycles the arbiter
spends prioritizing the high-priority side. The latter is the total number
of stall cycles after which the counter is cleared, meaning that the
arbiter will spend priority_cnt_denominator-priority_cnt_numerator stall-cycles
prioritizing the low-priority side.
In other words, the arbiter will dedicate a fraction numerator/denominator
of the available bandwidth (on average) to the high priority side.

Hardware-wise the change is minimal, touching only how the counter works
and the CSRs.
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