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Fix snitch verilator tests #146

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Merged
DanielKellerM merged 2 commits into from
Jul 7, 2026
Merged

Fix snitch verilator tests #146

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28a7401
hw: Assign obi rsp in all control paths
gbellocchi Jul 3, 2026
31c1c6d
hw: Extend idma busy condition with axi write completion
gbellocchi Jul 3, 2026
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23 changes: 18 additions & 5 deletions src/frontend/inst64/idma_inst64_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@
localparam int unsigned NumDim = 32'd2;
localparam int unsigned BufferDepth = 32'd3;
localparam int unsigned NumRules = 32'd5;
localparam int unsigned AwInFlightCntWidth = (NumAxInFlight < 2) ? 32'd1 : $clog2(NumAxInFlight + 1);

Check warning on line 76 in src/frontend/inst64/idma_inst64_top.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L76 

Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]"  location:{path:"src/frontend/inst64/idma_inst64_top.sv"  range:{start:{line:76  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

// derived constants and types
localparam int unsigned StrbWidth = AxiDataWidth / 32'd8;
Expand Down Expand Up @@ -327,14 +328,26 @@
);

always_comb begin : gen_obi_response
if (obi_we_q[c]) begin
obi_write_rsp[c].r = obi_res_i[c].r;
end else begin
obi_read_rsp[c].r = obi_res_i[c].r;
assign obi_write_rsp[c].r = obi_res_i[c].r;
assign obi_read_rsp[c].r = obi_res_i[c].r;
end

logic [AwInFlightCntWidth-1:0] aw_inflight_q; // outstanding write counter
logic aw_hs, b_hs; // handshake signals
assign aw_hs = axi_req_o[c].aw_valid & axi_res_i[c].aw_ready;
assign b_hs = axi_res_i[c].b_valid & axi_req_o[c].b_ready;
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_aw_inflight
if (!rst_ni) begin
aw_inflight_q <= '0;
end else if (aw_hs & ~b_hs) begin
aw_inflight_q <= aw_inflight_q + 1'b1;
end else if (b_hs & ~aw_hs) begin
aw_inflight_q <= aw_inflight_q - 1'b1;
end
end

assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c];
// Keep the channel busy until the iDMA backend or midend are busy, or until there's at least one AXI B response to be received.
assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c] | (aw_inflight_q != '0);
end


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