[DRAFT] Dynamic allocation scheme

Bender.lock

@@ -1,16 +1,16 @@
 packages:
   apb:
-    revision: null
-    version: null
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
     source:
-      Path: hardware/deps/apb
+      Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: null
-    version: null
+    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
+    version: 0.39.2
     source:
-      Path: hardware/deps/axi
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -26,39 +26,39 @@ packages:
     - scm
     - tech_cells_generic
   cluster_interconnect:
-    revision: null
-    version: null
+    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
+    version: 1.2.1
     source:
-      Path: hardware/deps/cluster_interconnect
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
     - common_cells
   common_cells:
-    revision: null
-    version: null
+    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
+    version: 1.33.0
     source:
-      Path: hardware/deps/common_cells
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: null
-    version: null
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
-      Path: hardware/deps/common_verification
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   fpnew:
-    revision: null
+    revision: 9481d57c161bb160fd294eae07279082bff06698
     version: null
     source:
-      Path: hardware/deps/fpnew
+      Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
     - common_cells
     - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
-    revision: null
+    revision: 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
     version: null
     source:
-      Path: hardware/deps/fpu_div_sqrt_mvp
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
     - common_cells
   idma:
@@ -72,10 +72,10 @@ packages:
     - common_verification
     - register_interface
   register_interface:
-    revision: null
-    version: null
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
     source:
-      Path: hardware/deps/register_interface
+      Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
@@ -104,9 +104,9 @@ packages:
     - axi
     - common_cells
   tech_cells_generic:
-    revision: null
-    version: null
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Path: hardware/deps/tech_cells_generic
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
-    - common_verification
+    - common_verification

Bender.yml

@@ -14,12 +14,9 @@ dependencies:
   reqrsp_interface:     { path: "hardware/deps/reqrsp_interface"                                             }
   snitch:               { path: "hardware/deps/snitch"                                                       }
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
-  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
+  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: "9481d57"   }
   cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
 
-workspace:
-  checkout_dir: "./hardware/deps"
-
 export_include_dirs:
   - hardware/include
 
@@ -48,6 +45,7 @@ sources:
   # Level 5
   - hardware/src/ctrl_registers.sv
   # Level 6
+  - hardware/src/tc_sram_simwrapper.sv
   - hardware/src/mempool_system.sv
 
   - target: mempool_vsim
@@ -75,4 +73,4 @@ sources:
   - target: fpga
     files:
       # Level 1
-    - hardware/src/axi_rab_wrap.sv
+    - hardware/src/axi_rab_wrap.sv

Makefile

@@ -21,6 +21,8 @@ ISA_SIM_INSTALL_DIR   ?= ${INSTALL_DIR}/riscv-isa-sim
 LLVM_INSTALL_DIR      ?= ${INSTALL_DIR}/llvm
 HALIDE_INSTALL_DIR    ?= ${INSTALL_DIR}/halide
 BENDER_INSTALL_DIR    ?= ${INSTALL_DIR}/bender
+BENDER                ?= ${BENDER_INSTALL_DIR}/bender
+BENDER_ROOT 					?= $(ROOT_DIR)/hardware/deps
 VERILATOR_INSTALL_DIR ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_DIR       ?= ${ROOT_DIR}/${SOFTWARE_DIR}/riscv-tests
 
@@ -54,26 +56,11 @@ else
   CLANG_LDFLAGS  := ""
 endif
 
-# Default target
-all: toolchain riscv-isa-sim halide
+#############
+# Toolchain #
+#############
 
-# Halide
-halide:
-	mkdir -p $(HALIDE_INSTALL_DIR)
-	cd toolchain/halide && mkdir -p build && cd build; \
-	$(CMAKE) \
-		-DLLVM_DIR=$(LLVM_INSTALL_DIR)/lib/cmake/llvm \
-		-DCMAKE_INSTALL_PREFIX=$(HALIDE_INSTALL_DIR) \
-		-DCMAKE_INSTALL_LIBDIR=lib \
-		-DCMAKE_CXX_COMPILER=$(CXX) \
-		-DCMAKE_C_COMPILER=$(CC) \
-		-DWITH_PYTHON_BINDINGS=OFF \
-		-DCMAKE_BUILD_TYPE=Release \
-		.. && \
-	make -j4 all && \
-	make install
-
-# Toolchain
+# Compilers
 toolchain: tc-riscv-gcc tc-llvm
 
 tc-riscv-gcc:
@@ -102,10 +89,47 @@ tc-llvm:
 	make -j6 all && \
 	make install
 
-riscv-isa-sim: update_opcodes
+# Halide
+halide:
+	mkdir -p $(HALIDE_INSTALL_DIR)
+	cd toolchain/halide && mkdir -p build && cd build; \
+	$(CMAKE) \
+		-DLLVM_DIR=$(LLVM_INSTALL_DIR)/lib/cmake/llvm \
+		-DCMAKE_INSTALL_PREFIX=$(HALIDE_INSTALL_DIR) \
+		-DCMAKE_INSTALL_LIBDIR=lib \
+		-DCMAKE_CXX_COMPILER=$(CXX) \
+		-DCMAKE_C_COMPILER=$(CC) \
+		-DWITH_PYTHON_BINDINGS=OFF \
+		-DCMAKE_BUILD_TYPE=Release \
+		.. && \
+	make -j4 all && \
+	make install
+
+# Opcodes
+update-opcodes: software/runtime/encoding.h hardware/deps/snitch/src/riscv_instr.sv
+
+software/runtime/encoding.h: toolchain/riscv-opcodes/*
+	make -C toolchain/riscv-opcodes encoding_out.h
+	mv toolchain/riscv-opcodes/encoding_out.h $@
+	ln -fsr $@ toolchain/riscv-isa-sim/riscv/encoding.h
+	ln -fsr $@ software/riscv-tests/env/encoding.h #this will change when riscv-tests is a submodule
+
+hardware/deps/snitch/src/riscv_instr.sv: toolchain/riscv-opcodes/*
+	make -C toolchain/riscv-opcodes inst.sverilog
+	mv toolchain/riscv-opcodes/inst.sverilog $@
+
+toolchain/riscv-opcodes/*:
+	git submodule update --init --recursive -- toolchain/riscv-opcodes
+
+# Tracing
+riscv-isa-sim: update-opcodes
 	cd toolchain/riscv-isa-sim && mkdir -p build && cd build; \
 	../configure --prefix=$(ISA_SIM_INSTALL_DIR) && make && make install
 
+#########
+# Tests #
+#########
+
 # Unit tests for verification
 .PHONY: riscv-tests build-riscv-tests clean-riscv-tests
 
@@ -115,7 +139,7 @@ riscv-tests: build-riscv-tests
 	config=minpool make -C $(SOFTWARE_DIR) riscv-tests && \
 	config=minpool make -C hardware verilate_test
 
-build-riscv-tests: update_opcodes
+build-riscv-tests: update-opcodes
 	cd $(RISCV_TESTS_DIR); \
 	autoconf && ./configure --with-xlen=32 --prefix=$$(pwd)/target && \
 	make isa -j4 && make install && \
@@ -126,8 +150,13 @@ clean-riscv-tests:
 	$(MAKE) -C $(SOFTWARE_DIR) clean
 	$(MAKE) -C $(RISCV_TESTS_DIR) clean
 
+###################
+# HW Dependencies #
+###################
+
 # Bender
 bender: check-bender
+
 check-bender:
 	@if [ -x $(BENDER_INSTALL_DIR)/bender ]; then \
 		req="bender $(BENDER_VERSION)"; \
@@ -142,23 +171,25 @@ $(BENDER_INSTALL_DIR)/bender:
 	mkdir -p $(BENDER_INSTALL_DIR) && cd $(BENDER_INSTALL_DIR) && \
 	curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- $(BENDER_VERSION)
 
+# Update hardware dependencies for MemPool
+.PHONY: update-deps
+update-deps: check-bender
+	$(BENDER) checkout
+
+##############
+# Simulation #
+##############
+
 # Verilator
 verilator: $(VERILATOR_INSTALL_DIR)/bin/verilator
 $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
 	cd $<; unset VERILATOR_ROOT; \
 	autoconf && CC=$(CC) CXX=$(CXX) ./configure --prefix=$(VERILATOR_INSTALL_DIR) $(VERILATOR_CI) && \
 	make -j4 && make install
 
-# Update and patch hardware dependencies for MemPool
-# Previous changes will be stashed. Clear all the stashes with `git stash clear`
-.PHONY: update-deps
-update-deps: setup-dram
-	for dep in $(shell git config --file .gitmodules --get-regexp path \
-	| awk '/hardware/{ print $$2 }'); do \
-	  git -C $${dep} diff --quiet || { echo $${dep}; git -C $${dep} stash -u; }; \
-	  git submodule update --init --recursive -- $${dep}; \
-	done
-	git apply hardware/deps/patches/*
+###########
+# DRAMsys #
+###########
 
 # Build, update and patch the DRAMsys submodule
 $(eval DRAM_PATH=$(realpath $(shell git config --file .gitmodules --get-regexp dram_rtl_sim.path | awk '/hardware/{ print $$2 }')))
@@ -195,30 +226,18 @@ setup-dram: config-dram
 		make -j; \
 	fi
 
-# Helper targets
+##########
+# Helper #
+##########
+
 .PHONY: clean format apps
 
 apps:
 	make -C $(SOFTWARE_DIR) apps
 
-update_opcodes: software/runtime/encoding.h hardware/deps/snitch/src/riscv_instr.sv
-
-software/runtime/encoding.h: toolchain/riscv-opcodes/*
-	make -C toolchain/riscv-opcodes encoding_out.h
-	mv toolchain/riscv-opcodes/encoding_out.h $@
-	ln -fsr $@ toolchain/riscv-isa-sim/riscv/encoding.h
-	ln -fsr $@ software/riscv-tests/env/encoding.h #this will change when riscv-tests is a submodule
-
-hardware/deps/snitch/src/riscv_instr.sv: toolchain/riscv-opcodes/*
-	make -C toolchain/riscv-opcodes inst.sverilog
-	mv toolchain/riscv-opcodes/inst.sverilog $@
-
-toolchain/riscv-opcodes/*:
-	git submodule update --init --recursive -- toolchain/riscv-opcodes
-
 format:
 	$(ROOT_DIR)/scripts/run_clang_format.py --clang-format-executable=$(LLVM_INSTALL_DIR)/bin/clang-format -i -r $(ROOT_DIR)
 	find ./software/data -name '*.py' -exec autopep8 --in-place --aggressive {} +
 
-clean: clean-riscv-tests
-	rm -rf $(INSTALL_DIR)
+clean: clean-riscv-tests clean-deps
+	rm -rf $(INSTALL_DIR)

README.md

@@ -1,6 +1,10 @@
 [![ci](https://github.com/pulp-platform/mempool/actions/workflows/ci.yml/badge.svg)](https://github.com/pulp-platform/mempool/actions/workflows/ci.yml)
 [![lint](https://github.com/pulp-platform/mempool/actions/workflows/lint.yml/badge.svg)](https://github.com/pulp-platform/mempool/actions/workflows/lint.yml)
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)
+# MemPool Dynamic Allocation Scheme
+Dynamic Allocation Scheme (DAS), a flexible, adaptable, runtime-configurable address mapping technique. DAS remaps contiguous address spaces to physically adjacent memory banks based on the workload’s memory access patterns, placing the data physically close to PEs.
+
+This repository branch contains DAS extensions based on MemPool.
 
 # MemPool
 

config/config.mk

@@ -73,6 +73,12 @@ zquarterinx ?= 0
 # DivSqrt deactivated by default
 xDivSqrt ?= 0
 
+# Enable configurable addressing scheme in the heap
+das ?= 1
+num_das_partitions ?= 4
+# Size of DAS-heap per core
+das_mem_size ?= 2048
+
 # This parameter is only used for TeraPool configurations
 num_sub_groups_per_group ?= 1
 remote_group_latency_cycles ?= 7

config/terapool.mk

@@ -45,4 +45,4 @@ dmas_per_group ?= 4 # Brust Length = 16
 
 # L2 Banks/Channels
 l2_banks = 16
-l2_size  ?= 16777216 # 1000000
+l2_size  ?= 16777216 # 1000000