Qcom 6.18.y

README

@@ -16,3 +16,5 @@ several of them using the reStructuredText markup notation.
 Please read the Documentation/process/changes.rst file, as it contains the
 requirements for building and running the kernel, and information about
 the problems which may result by upgrading your kernel.
+
+

arch/arm64/boot/dts/qcom/Makefile

@@ -474,6 +474,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb
 
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-staging.dtbo
 
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-staging.dtbo
+
 qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb

arch/arm64/boot/dts/qcom/lemans-evk.dts

@@ -189,6 +189,22 @@
 				sound-dai = <&q6apm>;
 			};
 		};
+
+		dp0-dai-link {
+			link-name = "DisplayPort0 Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&mdss0_dp0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
 	};
 
 	vbus_supply_regulator_0: regulator-vbus-supply-0 {

arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso

@@ -9,14 +9,16 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
-&eeprom1 {
-	nvmem-layout {
-		mac_addr1: mac-addr@0 {
-			reg = <0x0 0x6>;
-		};
+&i2c15 {
+	eeprom1: eeprom@52 {
+		nvmem-layout {
+			mac_addr1: mac-addr@0 {
+				reg = <0x0 0x6>;
+			};
 
-		mac_addr2: mac-addr@6 {
-			reg = <0x6 0x6>;
+			mac_addr2: mac-addr@6 {
+				reg = <0x6 0x6>;
+			};
 		};
 	};
 };
@@ -42,7 +44,7 @@
 				nvmem-cell-names = "mac-address";
 				pinctrl-names = "default";
 				pinctrl-0 = <&napa_intn_wol_sig>;
-				phy-reset-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>;
+				phy-reset-gpios = <&expander5 0 GPIO_ACTIVE_LOW>;
 				reset-deassert-us = <20000>;
 			};
 		};

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-staging.dtso

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+	qep_vreg: qep_vreg {
+		compatible = "regulator-fixed";
+		regulator-name = "qep_vreg";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&pm7325_gpios 8 0>;
+		enable-active-high;
+	};
+
+	aqr_vreg: aqr_vreg {
+		compatible = "regulator-fixed";
+		regulator-name = "aqr_vreg";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&pm7250b_gpios 4 0>;
+		enable-active-high;
+	};
+};
+
+&pcie1_port0 {
+	pcie@0,0 {
+		pcie@3,0 {
+			qps615: pci@0,0 {
+				compatible = "pci1179,0220";
+				interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+				phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>;
+				phy-supply = <&aqr_vreg>;
+				reset-deassert-us = <221000>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			pci@0,1 {
+				compatible = "pci1179,0220";
+				interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+				phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>;
+				phy-supply = <&qep_vreg>;
+				reset-deassert-us = <20000>;
+			};
+		};
+	};
+};
+
+&pcie0_port {
+	pcie@0,0 {
+		pcie@3,0 {
+			pci@0,0 {
+				interrupts-extended = <&tlmm 136 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				pinctrl-names = "default";
+				pinctrl-0 = <&rtl_rc0_intn_wol_sig>;
+				phy-mode = "sgmii";
+				phy-reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>;
+				reset-deassert-us = <75000>;
+			};
+
+			pci@0,1 {
+				interrupts-extended = <&tlmm 142 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_rc0_intn_wol_sig>;
+				phy-reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+				phy-supply = <&qep_vreg>;
+				reset-deassert-us = <20000>;
+			};
+		};
+	};
+};
+
+&tlmm {
+	qps615_intn_wol {
+		aqr_intn_wol_sig: aqr_intn_wol_sig {
+			pins = "gpio141";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+
+		napa_intn_wol_sig: napa_intn_wol_sig {
+			pins = "gpio101";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+
+		rtl_rc0_intn_wol_sig: rtl_rc0_intn_wol_sig {
+			pins = "gpio136";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+
+		napa_rc0_intn_wol_sig: napa_rc0_intn_wol_sig {
+			pins = "gpio142";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+	};
+};

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts

@@ -775,6 +775,7 @@
 	lt9611_codec: hdmi-bridge@2b {
 		compatible = "lontium,lt9611uxc";
 		reg = <0x2b>;
+		#sound-dai-cells = <1>;
 
 		interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>;
 		reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>;
@@ -1331,6 +1332,9 @@
 	compatible = "qcom,qcs6490-rb3gen2-sndcard";
 	model = "QCS6490-RB3Gen2";
 
+	pinctrl-0 = <&mi2s1_data0>, <&mi2s1_mclk>, <&mi2s1_sclk>, <&mi2s1_ws>;
+	pinctrl-names = "default";
+
 	audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
 			"SpkrRight IN", "WSA_SPK2 OUT",
 			"VA DMIC0", "vdd-micb",
@@ -1370,6 +1374,38 @@
 			sound-dai = <&q6apm>;
 		};
 	};
+
+	mi2s1-playback-dai-link {
+		link-name = "Secondary MI2S Playback";
+
+		codec {
+			sound-dai = <&lt9611_codec 0>;
+		};
+
+		cpu {
+			sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	dp-dai-link {
+		link-name = "DisplayPort0 Playback";
+
+		codec {
+			sound-dai = <&mdss_dp>;
+		};
+
+		cpu {
+			sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
 };
 
 &spi3 {
@@ -1747,3 +1783,26 @@
 	compatible = "qcom,qcm6490-lpassaudiocc";
 	/delete-property/ power-domains;
 };
+
+&mi2s1_data0 {
+	drive-strength = <8>;
+	bias-disable;
+};
+
+&mi2s1_mclk {
+	drive-strength = <8>;
+	bias-disable;
+	output-high;
+};
+
+&mi2s1_sclk {
+	drive-strength = <8>;
+	bias-disable;
+	output-high;
+};
+
+&mi2s1_ws {
+	drive-strength = <8>;
+	bias-disable;
+	output-high;
+};

arch/arm64/boot/dts/qcom/sc7280.dtsi

@@ -191,9 +191,12 @@
 			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 		};
 
-		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 {
-			reg = <0x0 0x9cb80000 0x0 0x800000>;
-			no-map;
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x800000>;
 		};
 	};
 
@@ -5880,6 +5883,11 @@
 				function = "mi2s1_ws";
 			};
 
+			mi2s1_mclk: mi2s1-mclk-state {
+				pins = "gpio105";
+				function = "sec_mi2s";
+			};
+
 			pcie0_clkreq_n: pcie0-clkreq-n-state {
 				pins = "gpio88";
 				function = "pcie0_clkreqn";

arch/arm64/configs/prune.config

@@ -92,7 +92,6 @@
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_BCM54140_PHY is not set
 # CONFIG_MICROSEMI_PHY is not set
-# CONFIG_REALTEK_PHY is not set
 # CONFIG_ROCKCHIP_PHY is not set
 # CONFIG_DP83867_PHY is not set
 # CONFIG_DP83TD510_PHY is not set

arch/arm64/configs/qcom.config

@@ -11,6 +11,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_CFG80211_CERTIFICATION_ONUS=y
+CONFIG_CONNECTOR=y
 CONFIG_CORESIGHT_CORESIGHT_TNOC=m
 CONFIG_CORESIGHT_CTCU=m
 CONFIG_CORESIGHT_DUMMY=m
@@ -42,6 +43,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0
 # CONFIG_PM_WAKELOCKS_GC is not set
 CONFIG_PM=y
 CONFIG_POWERCAP=y
+CONFIG_PROC_EVENTS=y
 CONFIG_QCA808X_PHY=m
 CONFIG_QCOM_QMI_COOLING=y
 CONFIG_REMOTEPROC_THERMAL=y

drivers/i2c/busses/i2c-qcom-geni.c

@@ -831,8 +831,14 @@ static int geni_i2c_probe(struct platform_device *pdev)
 	spin_lock_init(&gi2c->lock);
 	platform_set_drvdata(pdev, gi2c);
 
-	/* Keep interrupts disabled initially to allow for low-power modes */
-	ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
+	/*
+	 * Keep interrupts disabled initially to allow for low-power modes.
+	 * IRQF_NO_SUSPEND: Keep IRQ enabled during suspend to handle I2C transfers
+	 *                  in noirq phase (e.g., from PCIe driver's noirq_resume).
+	 * IRQF_EARLY_RESUME: Enable IRQ early during resume sequence.
+	 */
+	ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq,
+			       IRQF_NO_AUTOEN | IRQF_NO_SUSPEND | IRQF_EARLY_RESUME,
 			       dev_name(dev), gi2c);
 	if (ret)
 		return dev_err_probe(dev, ret,
@@ -1044,6 +1050,20 @@ static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
 {
 	struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
+	int ret = 0;
+
+	/*
+	 * Resume hardware to handle I2C transfers from other drivers'
+	 * noirq_resume callbacks (e.g., PCIe driver).
+	 * pm_runtime_force_resume() properly handles PM state and usage_count.
+	 */
+	if (gi2c->suspended) {
+		ret = pm_runtime_force_resume(dev);
+		if (ret) {
+			dev_err(dev, "Failed to resume I2C during noirq: %d\n", ret);
+			return ret;
+		}
+	}
 
 	i2c_mark_adapter_resumed(&gi2c->adap);
 	return 0;