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fix: read ICSR volatile in SCB::vect_active() #664

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fix: read ICSR volatile in SCB::vect_active() #664

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4 changes: 4 additions & 0 deletions cortex-m/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- The code should be clippy clean on all supported configurations now.
- Add embedded-hal 1.0 delays.

### Fixed
- `SCB::vect_active()` now reads ICSR with a volatile access, preventing the load from being narrowed
to a byte read that faults on word-only ICSR models.

## [v0.7.7] - 2023-01-03

- Add missing documentation for `critical-section-single-core` feature added
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3 changes: 1 addition & 2 deletions cortex-m/src/peripheral/scb.rs
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Expand Up @@ -2,7 +2,6 @@

#[cfg(any(armv7m, armv8m))]
use core::arch::asm;
use core::ptr;
#[cfg(any(armv7m, armv8m))]
use core::sync::atomic::{Ordering, compiler_fence};
#[cfg(not(armv6m))]
Expand Down Expand Up @@ -175,7 +174,7 @@ impl SCB {
/// Returns the active exception number
#[inline]
pub fn vect_active() -> VectActive {
let icsr = unsafe { ptr::read(&(*SCB::PTR).icsr as *const _ as *const u32) };
let icsr = unsafe { (*SCB::PTR).icsr.read() };

// NOTE(unsafe): Assume correctly selected target.
unsafe { VectActive::from(icsr as u8).unwrap_unchecked() }
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