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VSD_PD

WEEK 1

Steps to invoke Openlane Mount the docker container Type ./flow.tcl -interactive to invoke openlane prompt Since the default openlane package available is 1.0.2 we will proceed with that. Prepare the design by mentioning which design you are going to run the openlane flow which will generate the required files and will set the required environmental variables which will be used by various tools from the synthesis flow. image

After running synthesis when checking the synthesis.log image image The flop count is 1613 cells out off 15762, which accounts to around 10.6% of the total cells. Below is the chip area calculated only based on the sizes of the cells used.

image

When checked the timing report generated during synthesis, the TNS is 0 and then the worst slack is 0.52 which is positive

PHASE 2: Now running Floorplan,it first checks where we have the blocks like sram or any macro and does preplacement and decap insertion, then it does the Power planning and generates the PDN Network. image Die area after floorplan with utilization of 45%

image image

When zoomed in we can see the below where vdd and gnd are connected through 2 lanes

image

Ram macro is generated by using a memory compiler provided by foundry and these macros act like blackbox in P&R which are usually placed first before starting the placement process and these macros are already validated and gds is generated which we will use directly in our design. In case of standard cells these are smaller individual blocks of cells which are logic gates. After running the sta in synthesis netlist: for min corner:

image For max corner: image

To fix this we will find the cells having higher fanout: The below highlighted buffer is causing a delay of 0.72 which we will replace with sky130_fd_sc hd_buf_8

image

Changing SYNTH_STRATEGY to DELAY 3 image

And re running synthesis, we get now tns as -73.08 and wns as -2.79 image

After running CTS: image

POST CTS TIMING SNAPSHOT: image

After going into openroad:

image image

When checking the timing after CTS:

image image image

Generating pdn:

image

PDN should be generated before routing as these will occupy the top layers such as met5 and met4 and will be treated as obstacle by the routing tool and it wont route any signal in that place.

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