GSE : Geometric Silicon Emitter

Hardware Acceleration for Clifford Algebra Primitives

Current Status: Cl(2,0) Euclidean

The repository currently provides a Cl(2,0) Geometric Product module.

• Inputs: 8-bit signed multivectors.
• Outputs: 18-bit signed result (to prevent overflow).
• Architecture: Optimized for DSP48 slice mapping on FPGAs.

Repository Structure

• src/: Python-based Verilog generation logic.
• rtl/: Generated Verilog modules.
• sim/: Verification testbenches.

Quickstart

To run the hardware simulation (requires iverilog):

cd sim
chmod +x run_sim.sh
./run_sim.sh