A reading list for SRAM-based Compute-In-Memory (CIM) research.

IHP26a TinyTapeout implementation of a RISC-V CPU with an integrated SRAM-based compute-in-memory (CIM) accelerator for performing efficient analog matrix multiplications.

Minimal PyTorch examples for the four-stage structural evolution from ANN to event-driven SNN: Stage 0 (baseline ANN) → Stage 1 (binarization) → Stage 2 (temporal expansion) → Stage 3 (temporal accumulation) → Stage 4 (reset & sparsity control).

DUB Sparsity for Crossbars

LLM inference SoC

PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers

Some experiments to perform parallel data operations (compute-in-memory) on a 1980ies DRAM chip controlled with a CH32V003 RISC-V MCU

Two brains on one analog substrate from ~80% unsupervised SCFF bulk + ~20% closed-form SLDA namer: the math model for a forward-only, on-chip continual learner. Behavioral simulation, no silicon. Draft 6.0 = the "baby neocortex," validated across 11 phases.

HyperMR: Efficient Hypergraph-enhanced Matrix Storage on Compute-in-Memory Architecture. This work is presented at SIGMOD 2025.

Visual system design interview atlas for backend, systems, hardware, embedded, and ACiM NPU design

Enable mask-free visual dubbing with robust generative bootstrapping for image editing and inpainting