Secure Multi-Party Computation (MPC) framework written in Go. Implements two-party garbled circuits (Yao) and the Goldreich-Micali-Wigderson (GMW) protocol for secure computation.

Espresso Logic Minimizer - Modernized Edition

Embedded domain-specific combinator library for the abstract assembly and automated synthesis of logical circuits.

Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.

Logical circuits course final project.

Simple simulator of logical circuits

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

This is my final project in the Logical Circuits course. In this project we designed a Smart Home Management System.

Hello there, welcome! This is a JavaScript algorithm that solves the 4x4 Karnaugh map. It is expandable to solve 2 and 3 variable tables as well, although it needs some slight changes not done yet.

Windows console application for validating truth tables

The Logic Circuits Laboratory project assignment for the first semester of 1404 at the University of Guilan, implemented with VHDL on the "Posedge LogiX1 megawing board - Rev 1.2" board from the Spartan6 family.

Material académico y práctico de la UDA Circuitos Lógicos (MIE.SD01.09) – Maestría en Ingeniería Eléctrica.

A JavaScript API to (visually) manage logical circuits

✔️ Bit, Bytes and Logical Gates Abstraction

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

UNI S3: a single digit logical ( BCD to 7Segment ) counter in Proteus