A Voting Approach for Adaptive Network-on-Chip Power-Gating
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Dec 14, 2022 - C++
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power-gating
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A modular, open-source Power Management Unit (PMU) integrated into the PULP Croc SoC — an open-source RISC-V SoC based on the CVE2 (Ibex) core. Implements clock gating and power gating via UPF (IEEE 1801), using a fully open-source RTL-to-GDSII flow.
systemverilog risc-v power-management open-source-hardware upf power-gating pulp-platform clock-gating croc-soc
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May 7, 2026 - SystemVerilog
Variations of a multi-bit generalized magnitude comparator for different area and timing.
serialization fpga rtl vlsi comparator verilog-hdl logic-circuit serial-port digital-design low-power xilinx-vivado power-gating fpga-programming vlsi-design rtl-design altera-quartus register-transfer-level
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Jun 26, 2025 - D
Researching on Multi/Many-core Power-gating based on Network-on-Chip
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Dec 25, 2017
The project uses an ML surrogate model (e.g., Random Forest) to instantly predict a decoder's PPA (Power, Performance, Area) based on design parameters optimizing trade-off, significantly boosting efficiency and enabling a faster, data-driven VLSI design flow .
machine-learning random-forest power-gating vlsi-design digital-circuit-optimization decoder-design low-power-electronics ppa-optimization
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Apr 24, 2026 - Python
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