Improve decoupling cap main-pin layout

[Iineman2]

Summary

• add a deterministic fast path for decoupling_caps partitions instead of sending tiny bypass-cap groups through the generic packer
• order caps by their strongly connected main-chip pin coordinate when that context is available, with natural chip-id fallback when it is not
• compute spacing from the chip body plus pin envelope so protruding pads cannot overlap in the generated row
• add focused solver coverage for x-side/y-side main-pin ordering, pin-envelope spacing, and fallback ordering
• pin circuit-to-svg to a version that exports the schematic simulation helper required by the existing test suite, making CI runnable again

/claim #15

Verification

• npm exec --yes bun -- test tests/PackInnerPartitionsSolver/decoupling-cap-main-pin-layout.test.ts
• npm exec --yes bun -- test
• npm exec --yes bun -- x tsc --noEmit
• npm exec --yes bun -- run build
• npm exec --yes bun -- x biome format package.json lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts tests/PackInnerPartitionsSolver/decoupling-cap-main-pin-layout.test.ts
• git diff --check

[vercel]

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[MattCrossingham]

Nice work on the CI fix and the deterministic layout, @Iineman2! I had a similar approach in #92, but yours is cleaner with the dependency pin. I've closed my layout PR to keep things tidy for the maintainers. Once yours is merged, I'll rebase my Trace Alignment logic (#98) on top of it so they work together.

[Iineman2]

Added an extra quality pass on the decoupling-cap layout work:

• decoupling-cap-only partitions now inherit the group's allowed power/ground nets from strongly connected main-chip pins, so the cap pins retain VCC/GND identity even when the main chip is excluded from the partition
• unrelated external nets are intentionally not copied into the cap partition
• cap ordering now prefers the positive-voltage main pin when a capacitor has both power and ground strong connections, which makes the layout more stable for real decap pin ordering
• added regression coverage for inherited decap nets and voltage-aware main-pin ordering

Local verification:

• npx --yes bun test tests\\ChipPartitionsSolver.test.ts tests\\PackInnerPartitionsSolver\\decoupling-cap-main-pin-layout.test.ts -> 10 pass
• npx --yes bun test -> 24 pass, 1 skip
• npx --yes bun x tsc --noEmit -> pass
• npx --yes bun run build -> pass
• git diff --check -> pass

CI after the latest push: test, format-check, and type-check are passing. The remaining red Vercel status is the usual tscircuit team authorization gate for fork PRs.