add riscv64 CPU compatibility

[Xeonacid]

Add a riscv64 branch that uses the Zihintpause pause instruction when the target enables it, otherwise falls back to a nop that is valid for the baseline ISA.

Read the Linux device-tree timebase-frequency value from procfs or sysfs as the counter frequency, and use rdtime for timestamps so both helpers use the RISC-V time counter units.

[tzcnt]

Thanks for your contribution!

[tzcnt]

@Xeonacid want to do me a favor and run the hwloc_topo example CMake target (source here) on your SG2042 and paste the output back here? I want to make sure that the CPU / cache topology is properly detected.

[Xeonacid]

@Xeonacid want to do me a favor and run the hwloc_topo example CMake target (source here) on your SG2042 and paste the output back here? I want to make sure that the CPU / cache topology is properly detected.

Sure!

# of NUMA nodes         : 1
# of physical processors: 64
# of logical processors : 64

Hybrid architecture?    : false
# of CPU kinds          : 1
# of PERFORMANCE cores  : 64

# of core groups        : 16
Group 0:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 0 1 2 3
Group 1:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 4 5 6 7
Group 2:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 8 9 10 11
Group 3:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 12 13 14 15
Group 4:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 16 17 18 19
Group 5:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 20 21 22 23
Group 6:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 24 25 26 27
Group 7:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 28 29 30 31
Group 8:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 32 33 34 35
Group 9:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 36 37 38 39
Group 10:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 40 41 42 43
Group 11:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 44 45 46 47
Group 12:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 48 49 50 51
Group 13:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 52 53 54 55
Group 14:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 56 57 58 59
Group 15:
  NUMA index            : 0
  CPU kind              : PERFORMANCE
  SMT level             : 1
  physical core indexes : 60 61 62 63

It seems corrrect. SG2042 has 64 phsyical cores and 1MB * 16Cluster L2 cache, and aligns with the hwloc-info -p output:

depth 0:            1 Machine (type #0)
 depth 1:           1 Package (type #1)
  depth 2:          2 Group0 (type #12)
   depth 3:         4 Group1 (type #12)
    depth 4:        16 L2Cache (type #5)
     depth 5:       64 L1dCache (type #4)
      depth 6:      64 L1iCache (type #9)
       depth 7:     64 Core (type #2)
        depth 8:    64 PU (type #3)

Thanks for your effort in supporting RISC-V!