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amd64: support klauspost/compress amd64 ops#15

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xushiwei merged 7 commits intoxgo-dev:mainfrom
zhouguangyuan0718:codex/amd64-setcs
May 6, 2026
Merged

amd64: support klauspost/compress amd64 ops#15
xushiwei merged 7 commits intoxgo-dev:mainfrom
zhouguangyuan0718:codex/amd64-setcs

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@zhouguangyuan0718 zhouguangyuan0718 commented May 5, 2026

Summary

  • add amd64 lowering support for MOVBLZX, MOVWLZX, MOVWQZX, MOVWQSX, TZCNTQ, BTSQ, BEXTRQ, BZHIQ, SARL, SHLB, JS, JNS, and JNA
  • keep byte-width register writes correct for Plan9-style ADDB/SHLB/SET* forms that target low-byte lanes through generic registers like R10, R11, and R12
  • extend regression coverage across mov/arith/branch/cmpbt helpers for the new aliases and bit-manipulation ops
  • verify every *amd64*.s file under /home/zgy/go/pkg/mod/github.com/klauspost/compress@v1.17.9 now has no remaining unsupported opcodes by static opcode-to-lowering comparison

Testing

  • go test ./... -run 'TestAMD64(CmpBtCoverage|MovSyscallAndCRC32Coverage|ArithmeticCoverage|BranchCoverageDeep|CtxAliasAndFPFallbackCoverage|SetCSUsesCarryFlag|SetGEUsesSignedFlag|ADCBUsesCarryFlag)$'
  • static scan of all *amd64*.s files under github.com/klauspost/compress@v1.17.9 now reports UNSUPPORTED: (none)

Notes

  • full go test ./... still hits existing unrelated failures in TestGoTranslateSignatureCoverage and TestStdlibHashCRC32_AMD64_Compile in this environment

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codecov Bot commented May 5, 2026

Codecov Report

❌ Patch coverage is 71.17647% with 147 lines in your changes missing coverage. Please review.
✅ Project coverage is 69.58%. Comparing base (4190291) to head (9a73d7e).

Files with missing lines Patch % Lines
amd64_lower_arith.go 72.44% 54 Missing and 27 partials ⚠️
amd64_ctx.go 71.55% 20 Missing and 13 partials ⚠️
amd64_lower_cmpbt.go 55.76% 20 Missing and 3 partials ⚠️
types.go 25.00% 6 Missing ⚠️
amd64_lower_mov.go 90.32% 3 Missing ⚠️
amd64_needed.go 0.00% 1 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main      #15      +/-   ##
==========================================
+ Coverage   69.55%   69.58%   +0.02%     
==========================================
  Files          57       57              
  Lines       16431    16871     +440     
==========================================
+ Hits        11429    11740     +311     
- Misses       3685     3777      +92     
- Partials     1317     1354      +37     
Flag Coverage Δ
unittests 69.58% <71.17%> (+0.02%) ⬆️

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Code Review

This pull request implements support for the SETCS (Set if Carry) instruction in the AMD64 backend. The changes include updating the arithmetic lowering logic to handle SETCS by loading the carry flag and adding a unit test to verify the implementation. A review comment suggests further improving instruction coverage by adding support for SETCC and SETNE, ensuring consistency with other conditional operations.

Comment thread amd64_lower_arith.go Outdated
return true, false, fmt.Errorf("amd64: unsupported bit op %s", op)

case "SETEQ", "SETGT", "SETHI":
case "SETEQ", "SETGT", "SETHI", "SETCS":
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medium

To improve arithmetic coverage and maintain consistency with the CMOVcc implementation (line 830), consider also adding support for SETCC (Carry Clear) and SETNE (Not Equal). These are common counterparts to SETCS and SETEQ which are already present in this block.

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The core implementation is correct and consistent with the existing pattern — SETCS is properly dispatched in both the outer case list and the inner flag-loading switch, and loadFlag(c.flagsCFSlot) is the right helper (same as CMOVQCS). A few test quality and minor style issues below.

Comment thread amd64_helper_edge_test.go Outdated
mustLower("SETEQ", Instr{Raw: "SETEQ AX", Args: []Operand{{Kind: OpReg, Reg: AX}}})
mustLower("SETGT", Instr{Raw: "SETGT ret+8(FP)", Args: []Operand{{Kind: OpFP, FPOffset: 8}}})
mustLower("SETHI", Instr{Raw: "SETHI BX", Args: []Operand{{Kind: OpReg, Reg: BX}}})
mustLower("SETCS", Instr{Raw: "SETCS AX", Args: []Operand{{Kind: OpReg, Reg: AX}}})
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Only the register-destination path is covered for SETCS. SETGT on the line above exercises both OpReg and OpFP ("SETGT ret+8(FP)"). Consider adding:

mustLower("SETCS", Instr{Raw: "SETCS ret+8(FP)", Args: []Operand{{Kind: OpFP, FPOffset: 8}}})

to keep the FP-result-slot path tested for this instruction too.

Comment thread amd64_helper_edge_test.go Outdated
Comment on lines +662 to +664
if err := c.storeReg(AX, "0"); err != nil {
t.Fatalf("storeReg(AX) error = %v", err)
}
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storeReg(AX, "0") is a no-op here. Because Func{} is passed with no instructions, emitEntryAllocas never allocates a slot for AX, so storeReg returns nil without emitting any IR. The error check is dead and the call implies a precondition being set that isn't. Either remove it or structure the fixture so AX actually has an allocated slot.

Comment thread amd64_helper_edge_test.go
for _, want := range []string{
"store i1 true, ptr %flags_cf",
"load i1, ptr %flags_cf",
"select i1 %",
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"select i1 %" matches any select i1 % in the whole builder output and doesn't verify that the selected condition came from %flags_cf. A stronger assertion (e.g. checking that the load temporary is the one used in the select) would make the test actually validate the carry-flag wiring rather than just that a select appeared somewhere.

Comment thread amd64_lower_arith.go
Comment on lines +816 to +817
case "SETCS":
cond = c.loadFlag(c.flagsCFSlot)
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The sibling cases (SETGT, SETHI) have inline comments explaining what flag they check and the condition it represents. A brief comment here (e.g. // CF=1: carry / unsigned below) would keep the code consistent and make the flag semantics self-documenting.

@zhouguangyuan0718 zhouguangyuan0718 changed the title amd64: support SETCS amd64: support SETCS and SETGE May 5, 2026
@zhouguangyuan0718 zhouguangyuan0718 changed the title amd64: support SETCS and SETGE amd64: support SETCS, SETGE, and ADCB May 5, 2026
@zhouguangyuan0718 zhouguangyuan0718 changed the title amd64: support SETCS, SETGE, and ADCB amd64: support huff0 decompress ops May 5, 2026
@zhouguangyuan0718 zhouguangyuan0718 changed the title amd64: support huff0 decompress ops amd64: support klauspost/compress amd64 ops May 5, 2026
@xushiwei xushiwei merged commit 7e1ccbc into xgo-dev:main May 6, 2026
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